1272343Sngie// SPDX-License-Identifier: GPL-2.0 2272343Sngie/* 3272343Sngie * Copyright 2008 Freescale Semiconductor, Inc. 4272343Sngie */ 5272343Sngie 6272343Sngie#include <common.h> 7272343Sngie#include <fsl_ddr_sdram.h> 8272343Sngie#include <log.h> 9272343Sngie#include <asm/bitops.h> 10272343Sngie 11272343Sngie#include <fsl_ddr.h> 12272343Sngie 13272343Sngie/* 14272343Sngie * Calculate the Density of each Physical Rank. 15272343Sngie * Returned size is in bytes. 16272343Sngie * 17272343Sngie * Study these table from Byte 31 of JEDEC SPD Spec. 18272343Sngie * 19272343Sngie * DDR I DDR II 20272343Sngie * Bit Size Size 21272343Sngie * --- ----- ------ 22272343Sngie * 7 high 512MB 512MB 23272343Sngie * 6 256MB 256MB 24272343Sngie * 5 128MB 128MB 25272343Sngie * 4 64MB 16GB 26272343Sngie * 3 32MB 8GB 27272343Sngie * 2 16MB 4GB 28272343Sngie * 1 2GB 2GB 29272343Sngie * 0 low 1GB 1GB 30272343Sngie * 31272343Sngie * Reorder Table to be linear by stripping the bottom 32272343Sngie * 2 or 5 bits off and shifting them up to the top. 33272343Sngie */ 34272343Sngie 35272343Sngiestatic unsigned long long 36272343Sngiecompute_ranksize(unsigned int mem_type, unsigned char row_dens) 37272343Sngie{ 38272343Sngie unsigned long long bsize; 39272343Sngie 40272343Sngie /* Bottom 2 bits up to the top. */ 41272343Sngie bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)); 42272343Sngie bsize <<= 24ULL; 43272343Sngie debug("DDR: DDR I rank density = 0x%16llx\n", bsize); 44272343Sngie 45272343Sngie return bsize; 46272343Sngie} 47272343Sngie 48272343Sngie/* 49272343Sngie * Convert a two-nibble BCD value into a cycle time. 50272343Sngie * While the spec calls for nano-seconds, picos are returned. 51272343Sngie * 52272343Sngie * This implements the tables for bytes 9, 23 and 25 for both 53272343Sngie * DDR I and II. No allowance for distinguishing the invalid 54272343Sngie * fields absent for DDR I yet present in DDR II is made. 55272343Sngie * (That is, cycle times of .25, .33, .66 and .75 ns are 56272343Sngie * allowed for both DDR II and I.) 57272343Sngie */ 58272343Sngiestatic unsigned int 59272343Sngieconvert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) 60272343Sngie{ 61272343Sngie /* Table look up the lower nibble, allow DDR I & II. */ 62272343Sngie unsigned int tenths_ps[16] = { 63272343Sngie 0, 64272343Sngie 100, 65272343Sngie 200, 66272343Sngie 300, 67272343Sngie 400, 68272343Sngie 500, 69272343Sngie 600, 70272343Sngie 700, 71272343Sngie 800, 72272343Sngie 900, 73272343Sngie 250, /* This and the next 3 entries valid ... */ 74272343Sngie 330, /* ... only for tCK calculations. */ 75272343Sngie 660, 76272343Sngie 750, 77272343Sngie 0, /* undefined */ 78272343Sngie 0 /* undefined */ 79272343Sngie }; 80272343Sngie 81272343Sngie unsigned int whole_ns = (spd_val & 0xF0) >> 4; 82272343Sngie unsigned int tenth_ns = spd_val & 0x0F; 83272343Sngie unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; 84272343Sngie 85272343Sngie return ps; 86272343Sngie} 87272343Sngie 88272343Sngiestatic unsigned int 89272343Sngieconvert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) 90272343Sngie{ 91272343Sngie unsigned int tenth_ns = (spd_val & 0xF0) >> 4; 92272343Sngie unsigned int hundredth_ns = spd_val & 0x0F; 93272343Sngie unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; 94272343Sngie 95272343Sngie return ps; 96272343Sngie} 97272343Sngie 98272343Sngiestatic unsigned int byte40_table_ps[8] = { 99272343Sngie 0, 100272343Sngie 250, 101272343Sngie 330, 102272343Sngie 500, 103272343Sngie 660, 104272343Sngie 750, 105272343Sngie 0, /* supposed to be RFC, but not sure what that means */ 106272343Sngie 0 /* Undefined */ 107272343Sngie}; 108272343Sngie 109272343Sngiestatic unsigned int 110272343Sngiecompute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) 111272343Sngie{ 112272343Sngie return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000 113272343Sngie + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; 114272343Sngie} 115272343Sngie 116272343Sngiestatic unsigned int 117272343Sngiecompute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) 118272343Sngie{ 119272343Sngie return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; 120272343Sngie} 121272343Sngie 122272343Sngie/* 123272343Sngie * tCKmax from DDR I SPD Byte 43 124272343Sngie * 125272343Sngie * Bits 7:2 == whole ns 126272343Sngie * Bits 1:0 == quarter ns 127272343Sngie * 00 == 0.00 ns 128272343Sngie * 01 == 0.25 ns 129272343Sngie * 10 == 0.50 ns 130272343Sngie * 11 == 0.75 ns 131272343Sngie * 132272343Sngie * Returns picoseconds. 133272343Sngie */ 134272343Sngiestatic unsigned int 135272343Sngiecompute_tckmax_from_spd_ps(unsigned int byte43) 136272343Sngie{ 137272343Sngie return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250; 138272343Sngie} 139272343Sngie 140272343Sngie/* 141272343Sngie * Determine Refresh Rate. Ignore self refresh bit on DDR I. 142272343Sngie * Table from SPD Spec, Byte 12, converted to picoseconds and 143272343Sngie * filled in with "default" normal values. 144272343Sngie */ 145272343Sngiestatic unsigned int 146272343Sngiedetermine_refresh_rate_ps(const unsigned int spd_refresh) 147272343Sngie{ 148272343Sngie unsigned int refresh_time_ps[8] = { 149272343Sngie 15625000, /* 0 Normal 1.00x */ 150272343Sngie 3900000, /* 1 Reduced .25x */ 151272343Sngie 7800000, /* 2 Extended .50x */ 152272343Sngie 31300000, /* 3 Extended 2.00x */ 153272343Sngie 62500000, /* 4 Extended 4.00x */ 154272343Sngie 125000000, /* 5 Extended 8.00x */ 155272343Sngie 15625000, /* 6 Normal 1.00x filler */ 156272343Sngie 15625000, /* 7 Normal 1.00x filler */ 157272343Sngie }; 158272343Sngie 159272343Sngie return refresh_time_ps[spd_refresh & 0x7]; 160272343Sngie} 161272343Sngie 162272343Sngie/* 163272343Sngie * The purpose of this function is to compute a suitable 164272343Sngie * CAS latency given the DRAM clock period. The SPD only 165272343Sngie * defines at most 3 CAS latencies. Typically the slower in 166 * frequency the DIMM runs at, the shorter its CAS latency can be. 167 * If the DIMM is operating at a sufficiently low frequency, 168 * it may be able to run at a CAS latency shorter than the 169 * shortest SPD-defined CAS latency. 170 * 171 * If a CAS latency is not found, 0 is returned. 172 * 173 * Do this by finding in the standard speed bin table the longest 174 * tCKmin that doesn't exceed the value of mclk_ps (tCK). 175 * 176 * An assumption made is that the SDRAM device allows the 177 * CL to be programmed for a value that is lower than those 178 * advertised by the SPD. This is not always the case, 179 * as those modes not defined in the SPD are optional. 180 * 181 * CAS latency de-rating based upon values JEDEC Standard No. 79-E 182 * Table 11. 183 * 184 * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2 185 */ 186 /* CL2.0 CL2.5 CL3.0 */ 187unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 }; 188 189unsigned int 190compute_derated_DDR1_CAS_latency(unsigned int mclk_ps) 191{ 192 const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins); 193 unsigned int lowest_tCKmin_found = 0; 194 unsigned int lowest_tCKmin_CL = 0; 195 unsigned int i; 196 197 debug("mclk_ps = %u\n", mclk_ps); 198 199 for (i = 0; i < num_speed_bins; i++) { 200 unsigned int x = ddr1_speed_bins[i]; 201 debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", 202 i, x, lowest_tCKmin_found); 203 if (x && lowest_tCKmin_found <= x && x <= mclk_ps) { 204 lowest_tCKmin_found = x; 205 lowest_tCKmin_CL = i + 1; 206 } 207 } 208 209 debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); 210 211 return lowest_tCKmin_CL; 212} 213 214/* 215 * ddr_compute_dimm_parameters for DDR1 SPD 216 * 217 * Compute DIMM parameters based upon the SPD information in spd. 218 * Writes the results to the dimm_params_t structure pointed by pdimm. 219 * 220 * FIXME: use #define for the retvals 221 */ 222unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, 223 const ddr1_spd_eeprom_t *spd, 224 dimm_params_t *pdimm, 225 unsigned int dimm_number) 226{ 227 unsigned int retval; 228 229 if (spd->mem_type) { 230 if (spd->mem_type != SPD_MEMTYPE_DDR) { 231 printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number); 232 return 1; 233 } 234 } else { 235 memset(pdimm, 0, sizeof(dimm_params_t)); 236 return 1; 237 } 238 239 retval = ddr1_spd_check(spd); 240 if (retval) { 241 printf("DIMM %u: failed checksum\n", dimm_number); 242 return 2; 243 } 244 245 /* 246 * The part name in ASCII in the SPD EEPROM is not null terminated. 247 * Guarantee null termination here by presetting all bytes to 0 248 * and copying the part name in ASCII from the SPD onto it 249 */ 250 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 251 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); 252 253 /* DIMM organization parameters */ 254 pdimm->n_ranks = spd->nrows; 255 pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens); 256 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; 257 pdimm->data_width = spd->dataw_lsb; 258 pdimm->primary_sdram_width = spd->primw; 259 pdimm->ec_sdram_width = spd->ecw; 260 261 /* 262 * FIXME: Need to determine registered_dimm status. 263 * 1 == register buffered 264 * 0 == unbuffered 265 */ 266 pdimm->registered_dimm = 0; /* unbuffered */ 267 268 /* SDRAM device parameters */ 269 pdimm->n_row_addr = spd->nrow_addr; 270 pdimm->n_col_addr = spd->ncol_addr; 271 pdimm->n_banks_per_sdram_device = spd->nbanks; 272 pdimm->edc_config = spd->config; 273 pdimm->burst_lengths_bitmask = spd->burstl; 274 275 /* 276 * Calculate the Maximum Data Rate based on the Minimum Cycle time. 277 * The SPD clk_cycle field (tCKmin) is measured in tenths of 278 * nanoseconds and represented as BCD. 279 */ 280 pdimm->tckmin_x_ps 281 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); 282 pdimm->tckmin_x_minus_1_ps 283 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); 284 pdimm->tckmin_x_minus_2_ps 285 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); 286 287 pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax); 288 289 /* 290 * Compute CAS latencies defined by SPD 291 * The SPD caslat_x should have at least 1 and at most 3 bits set. 292 * 293 * If cas_lat after masking is 0, the __ilog2 function returns 294 * 255 into the variable. This behavior is abused once. 295 */ 296 pdimm->caslat_x = __ilog2(spd->cas_lat); 297 pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat 298 & ~(1 << pdimm->caslat_x)); 299 pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat 300 & ~(1 << pdimm->caslat_x) 301 & ~(1 << pdimm->caslat_x_minus_1)); 302 303 /* Compute CAS latencies below that defined by SPD */ 304 pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency( 305 get_memory_clk_period_ps(ctrl_num)); 306 307 /* Compute timing parameters */ 308 pdimm->trcd_ps = spd->trcd * 250; 309 pdimm->trp_ps = spd->trp * 250; 310 pdimm->tras_ps = spd->tras * 1000; 311 312 pdimm->twr_ps = mclk_to_picos(ctrl_num, 3); 313 pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1); 314 pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc); 315 316 pdimm->trrd_ps = spd->trrd * 250; 317 pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc); 318 319 pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); 320 321 pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); 322 pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); 323 pdimm->tds_ps 324 = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); 325 pdimm->tdh_ps 326 = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); 327 328 pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */ 329 pdimm->tdqsq_max_ps = spd->tdqsq * 10; 330 pdimm->tqhs_ps = spd->tqhs * 10; 331 332 return 0; 333} 334