1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Clock drivers for Qualcomm sm6115 (and sm4250/qrb4210) 4 * 5 * Copyright (c) 2024 Linaro Ltd. 6 * 7 */ 8 9#include <clk-uclass.h> 10#include <dm.h> 11#include <linux/delay.h> 12#include <asm/io.h> 13#include <linux/bitops.h> 14#include <linux/bug.h> 15#include <dt-bindings/clock/qcom,gcc-sm6115.h> 16 17#include "clock-qcom.h" 18 19#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608 20#define SDCC1_APPS_CLK_CMD_RCGR 0x38028 21#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c 22 23static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 24 F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625), 25 F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625), 26 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), 27 F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625), 28 F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75), 29 F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25), 30 F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75), 31 F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0), 32 F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15), 33 F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25), 34 F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), 35 F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375), 36 F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75), 37 F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625), 38 F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0), 39 F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0), 40 {} 41}; 42 43static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 44 F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), 45 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), 46 F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0), 47 F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0), 48 F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), 49 F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), 50 {} 51}; 52 53static const struct pll_vote_clk gpll0_clk = { 54 .status = 0, 55 .status_bit = BIT(31), 56 .ena_vote = 0x79000, 57 .vote_bit = BIT(0), 58}; 59 60static const struct gate_clk sm6115_clks[] = { 61 GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, 0x00000001), 62 GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, 0x00000200), 63 GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, 0x00000100), 64 GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, 0x00000400), 65 GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, 0x00000800), 66 GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, 0x00001000), 67 GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, 0x00002000), 68 GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, 0x00004000), 69 GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, 0x00008000), 70 GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, 0x00000040), 71 GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, 0x00000080), 72 GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, 0x00000001), 73 GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, 0x00000001), 74 GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, 0x00000001), 75 GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, 0x00000001), 76 GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, 0x00000001), 77 GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, 0x00000001), 78 GATE_CLK(GCC_SYS_NOC_UFS_PHY_AXI_CLK, 0x45098, 0x00000001), 79 GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, 0x00000001), 80 GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x45014, 0x00000001), 81 GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x45010, 0x00000001), 82 GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x45044, 0x00000001), 83 GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x45078, 0x00000001), 84 GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x4501c, 0x00000001), 85 GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x45018, 0x00000001), 86 GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x45040, 0x00000001), 87 GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, 0x00000001), 88 GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, 0x00000001), 89 GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, 0x00000001), 90 GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x9f000, 0x00000001), 91 GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, 0x00000001), 92 GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, 0x00000001), 93 GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, 0x00000001), 94 GATE_CLK(GCC_UFS_CLKREF_CLK, 0x8c000, 0x00000001), 95}; 96 97static ulong sm6115_set_rate(struct clk *clk, ulong rate) 98{ 99 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 100 const struct freq_tbl *freq; 101 102 debug("%s: clk %s rate %lu\n", __func__, sm6115_clks[clk->id].name, 103 rate); 104 105 switch (clk->id) { 106 case GCC_QUPV3_WRAP0_S4_CLK: /*UART2*/ 107 freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); 108 clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR, 109 freq->pre_div, freq->m, freq->n, freq->src, 110 16); 111 return 0; 112 case GCC_SDCC2_APPS_CLK: 113 /* Enable GPLL7 so we can point SDCC2_APPS_CLK_SRC RCG at it */ 114 clk_enable_gpll0(priv->base, &gpll0_clk); 115 freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); 116 WARN(freq->src != CFG_CLK_SRC_GPLL0, 117 "SDCC2_APPS_CLK_SRC not set to GPLL0, requested rate %lu\n", 118 rate); 119 clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, 120 freq->pre_div, freq->m, freq->n, freq->src, 121 8); 122 return freq->freq; 123 case GCC_SDCC1_APPS_CLK: 124 /* The firmware turns this on for us and always sets it to this rate */ 125 return 384000000; 126 default: 127 return rate; 128 } 129} 130 131static int sm6115_enable(struct clk *clk) 132{ 133 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 134 135 if (priv->data->num_clks < clk->id) { 136 debug("%s: unknown clk id %lu\n", __func__, clk->id); 137 return 0; 138 } 139 140 debug("%s: clk %s\n", __func__, sm6115_clks[clk->id].name); 141 142 switch (clk->id) { 143 case GCC_USB30_PRIM_MASTER_CLK: 144 qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); 145 qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK); 146 break; 147 } 148 149 qcom_gate_clk_en(priv, clk->id); 150 151 return 0; 152} 153 154static const struct qcom_reset_map sm6115_gcc_resets[] = { 155 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 156 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 157 [GCC_SDCC1_BCR] = { 0x38000 }, 158 [GCC_SDCC2_BCR] = { 0x1e000 }, 159 [GCC_UFS_PHY_BCR] = { 0x45000 }, 160 [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 161 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 162 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 163 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 164 [GCC_VCODEC0_BCR] = { 0x58094 }, 165 [GCC_VENUS_BCR] = { 0x58078 }, 166 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 167}; 168 169static const struct qcom_power_map sm6115_gdscs[] = { 170 [GCC_USB30_PRIM_GDSC] = { 0x1a004 }, 171}; 172 173static struct msm_clk_data sm6115_gcc_data = { 174 .resets = sm6115_gcc_resets, 175 .num_resets = ARRAY_SIZE(sm6115_gcc_resets), 176 .clks = sm6115_clks, 177 .num_clks = ARRAY_SIZE(sm6115_clks), 178 .power_domains = sm6115_gdscs, 179 .num_power_domains = ARRAY_SIZE(sm6115_gdscs), 180 181 .enable = sm6115_enable, 182 .set_rate = sm6115_set_rate, 183}; 184 185static const struct udevice_id gcc_sm6115_of_match[] = { 186 { 187 .compatible = "qcom,gcc-sm6115", 188 .data = (ulong)&sm6115_gcc_data, 189 }, 190 {} 191}; 192 193U_BOOT_DRIVER(gcc_sm6115) = { 194 .name = "gcc_sm6115", 195 .id = UCLASS_NOP, 196 .of_match = gcc_sm6115_of_match, 197 .bind = qcom_cc_bind, 198 .flags = DM_FLAG_PRE_RELOC, 199}; 200