1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Clock drivers for Qualcomm qcm2290 4 * 5 * (C) Copyright 2024 Linaro Ltd. 6 */ 7 8#include <clk-uclass.h> 9#include <dm.h> 10#include <linux/delay.h> 11#include <asm/io.h> 12#include <linux/bug.h> 13#include <linux/bitops.h> 14#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 15 16#include "clock-qcom.h" 17 18#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608 19#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c 20 21static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 22 F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625), 23 F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625), 24 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), 25 F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625), 26 F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75), 27 F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25), 28 F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75), 29 F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0), 30 F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15), 31 F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25), 32 F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), 33 F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375), 34 F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75), 35 F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625), 36 F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0), 37 F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0), 38 {} 39}; 40 41static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 42 F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), 43 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), 44 F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0), 45 F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0), 46 F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), 47 F(202000000, CFG_CLK_SRC_GPLL7, 4, 0, 0), // 6.5, 1, 4 48 {} 49}; 50 51static const struct pll_vote_clk gpll7_clk = { 52 .status = 0x7000, 53 .status_bit = BIT(31), 54 .ena_vote = 0x79000, 55 .vote_bit = BIT(7), 56}; 57 58static const struct gate_clk qcm2290_clks[] = { 59 GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, 0x00000001), 60 GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, 0x00000001), 61 GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, 0x00000200), 62 GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, 0x00000100), 63 GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, 0x00000400), 64 GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, 0x00000800), 65 GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, 0x00001000), 66 GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, 0x00002000), 67 GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, 0x00004000), 68 GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, 0x00008000), 69 GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, 0x00000040), 70 GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, 0x00000080), 71 GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, 0x00000001), 72 GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, 0x00000001), 73 GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, 0x00000001), 74 GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, 0x00000001), 75 GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, 0x00000001), 76 GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, 0x00000001), 77 GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, 0x00000001), 78 GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, 0x00000001), 79 GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, 0x00000001), 80 GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, 0x00000001), 81 GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x9f000, 0x00000001), 82 GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, 0x00000001), 83 GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, 0x00000001), 84}; 85 86static ulong qcm2290_set_rate(struct clk *clk, ulong rate) 87{ 88 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 89 const struct freq_tbl *freq; 90 91 debug("%s: clk %s rate %lu\n", __func__, clk->dev->name, rate); 92 93 switch (clk->id) { 94 case GCC_QUPV3_WRAP0_S4_CLK: /*UART2*/ 95 freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); 96 clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR, 97 freq->pre_div, freq->m, freq->n, freq->src, 98 16); 99 return 0; 100 case GCC_SDCC2_APPS_CLK: 101 /* Enable GPLL7 so we can point SDCC2_APPS_CLK_SRC RCG at it */ 102 clk_enable_gpll0(priv->base, &gpll7_clk); 103 freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); 104 WARN(freq->src != CFG_CLK_SRC_GPLL7, 105 "SDCC2_APPS_CLK_SRC not set to GPLL7, requested rate %lu\n", 106 rate); 107 clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, 108 freq->pre_div, freq->m, freq->n, freq->src, 109 8); 110 return freq->freq; 111 case GCC_SDCC1_APPS_CLK: 112 /* The firmware turns this on for us and always sets it to this rate */ 113 return 384000000; 114 default: 115 return 0; 116 } 117} 118 119static int qcm2290_enable(struct clk *clk) 120{ 121 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 122 123 if (priv->data->num_clks < clk->id) { 124 debug("%s: unknown clk id %lu\n", __func__, clk->id); 125 return 0; 126 } 127 128 debug("%s: clk %s\n", __func__, qcm2290_clks[clk->id].name); 129 130 switch (clk->id) { 131 case GCC_USB30_PRIM_MASTER_CLK: 132 qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); 133 qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK); 134 break; 135 } 136 137 qcom_gate_clk_en(priv, clk->id); 138 139 return 0; 140} 141 142static const struct qcom_reset_map qcm2290_gcc_resets[] = { 143 [GCC_CAMSS_OPE_BCR] = { 0x55000 }, 144 [GCC_CAMSS_TFE_BCR] = { 0x52000 }, 145 [GCC_CAMSS_TOP_BCR] = { 0x58000 }, 146 [GCC_GPU_BCR] = { 0x36000 }, 147 [GCC_MMSS_BCR] = { 0x17000 }, 148 [GCC_PDM_BCR] = { 0x20000 }, 149 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, 150 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 151 [GCC_SDCC1_BCR] = { 0x38000 }, 152 [GCC_SDCC2_BCR] = { 0x1e000 }, 153 [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 154 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 155 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 156 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 157 [GCC_VCODEC0_BCR] = { 0x58094 }, 158 [GCC_VENUS_BCR] = { 0x58078 }, 159 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 160}; 161 162static const struct qcom_power_map qcm2290_gdscs[] = { 163 [GCC_USB30_PRIM_GDSC] = { 0x1a004 }, 164}; 165 166static struct msm_clk_data qcm2290_gcc_data = { 167 .resets = qcm2290_gcc_resets, 168 .num_resets = ARRAY_SIZE(qcm2290_gcc_resets), 169 .clks = qcm2290_clks, 170 .num_clks = ARRAY_SIZE(qcm2290_clks), 171 .power_domains = qcm2290_gdscs, 172 .num_power_domains = ARRAY_SIZE(qcm2290_gdscs), 173 174 .enable = qcm2290_enable, 175 .set_rate = qcm2290_set_rate, 176}; 177 178static const struct udevice_id gcc_qcm2290_of_match[] = { 179 { 180 .compatible = "qcom,gcc-qcm2290", 181 .data = (ulong)&qcm2290_gcc_data, 182 }, 183 {} 184}; 185 186U_BOOT_DRIVER(gcc_qcm2290) = { 187 .name = "gcc_qcm2290", 188 .id = UCLASS_NOP, 189 .of_match = gcc_qcm2290_of_match, 190 .bind = qcom_cc_bind, 191 .flags = DM_FLAG_PRE_RELOC, 192}; 193