1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Samsung Exynos850 clock driver. 4 * Copyright (c) 2023 Linaro Ltd. 5 * Author: Sam Protsenko <semen.protsenko@linaro.org> 6 */ 7 8#include <dm.h> 9#include <asm/io.h> 10#include <dt-bindings/clock/exynos850.h> 11#include "clk.h" 12 13enum exynos850_cmu_id { 14 CMU_TOP, 15 CMU_PERI, 16 CMU_CORE, 17 CMU_HSI, 18}; 19 20/* ---- CMU_TOP ------------------------------------------------------------- */ 21 22/* Register Offset definitions for CMU_TOP (0x120e0000) */ 23#define PLL_CON0_PLL_MMC 0x0100 24#define PLL_CON3_PLL_MMC 0x010c 25#define PLL_CON0_PLL_SHARED0 0x0140 26#define PLL_CON3_PLL_SHARED0 0x014c 27#define PLL_CON0_PLL_SHARED1 0x0180 28#define PLL_CON3_PLL_SHARED1 0x018c 29#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 30#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 31#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 32#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 33#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 34#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 35#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 36#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 37#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 38#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 39#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 40#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 41#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 42#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 43#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 44#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 45#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 46#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 47#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 48#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 49#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 50#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 51#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 52#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 53#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 54#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 55#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 56#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 57#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 58#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 59#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 60#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 61#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 62#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 63#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 64#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 65 66/* List of parent clocks for Muxes in CMU_TOP: for PURECLKCOMP */ 67PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" }; 68PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" }; 69PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" }; 70/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 71PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 72 "dout_shared1_div3", "dout_shared0_div4" }; 73PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 74 "dout_shared0_div3", "dout_shared1_div3" }; 75PNAME(mout_core_mmc_embd_p) = { "clock-oscclk", "dout_shared0_div2", 76 "dout_shared1_div2", "dout_shared0_div3", 77 "dout_shared1_div3", "mout_mmc_pll", 78 "clock-oscclk", "clock-oscclk" }; 79PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 80 "dout_shared0_div4", "dout_shared1_div4" }; 81/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 82PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 83PNAME(mout_hsi_mmc_card_p) = { "clock-oscclk", "dout_shared0_div2", 84 "dout_shared1_div2", "dout_shared0_div3", 85 "dout_shared1_div3", "mout_mmc_pll", 86 "clock-oscclk", "clock-oscclk" }; 87PNAME(mout_hsi_usb20drd_p) = { "clock-oscclk", "dout_shared0_div4", 88 "dout_shared1_div4", "clock-oscclk" }; 89/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 90PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 91PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4", 92 "dout_shared1_div4", "clock-oscclk" }; 93PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4", 94 "dout_shared1_div4", "clock-oscclk" }; 95 96/* PURECLKCOMP */ 97 98static const struct samsung_pll_clock top_pure_pll_clks[] = { 99 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk", 100 PLL_CON3_PLL_SHARED0), 101 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk", 102 PLL_CON3_PLL_SHARED1), 103 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk", 104 PLL_CON3_PLL_MMC), 105}; 106 107static const struct samsung_mux_clock top_pure_mux_clks[] = { 108 MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 109 PLL_CON0_PLL_SHARED0, 4, 1), 110 MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 111 PLL_CON0_PLL_SHARED1, 4, 1), 112 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 113 PLL_CON0_PLL_MMC, 4, 1), 114}; 115 116static const struct samsung_div_clock top_pure_div_clks[] = { 117 DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 118 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 119 DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 120 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 121 DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 122 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 123 DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 124 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 125 DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 126 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 127 DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 128 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 129}; 130 131/* CORE */ 132 133static const struct samsung_mux_clock top_core_mux_clks[] = { 134 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 135 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 136 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 137 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 138 MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 139 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 140 MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 141 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 142}; 143 144static const struct samsung_gate_clock top_core_gate_clks[] = { 145 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 146 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 147 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 148 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 149 GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 150 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 151 GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 152 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 153}; 154 155static const struct samsung_div_clock top_core_div_clks[] = { 156 DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 157 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 158 DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 159 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 160 DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 161 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 162 DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 163 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 164}; 165 166/* HSI */ 167 168static const struct samsung_mux_clock top_hsi_mux_clks[] = { 169 MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 170 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 171 MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 172 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 173 MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 174 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 175}; 176 177static const struct samsung_gate_clock top_hsi_gate_clks[] = { 178 GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 179 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 180 GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 181 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 182 GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 183 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 184}; 185 186static const struct samsung_div_clock top_hsi_div_clks[] = { 187 DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 188 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 189 DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 190 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 191 DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 192 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 193}; 194 195/* PERI */ 196 197static const struct samsung_mux_clock top_peri_mux_clks[] = { 198 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 199 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 200 MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 201 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 202 MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 203 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 204}; 205 206static const struct samsung_gate_clock top_peri_gate_clks[] = { 207 GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 208 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 209 GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 210 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 211 GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 212 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 213}; 214 215static const struct samsung_div_clock top_peri_div_clks[] = { 216 DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 217 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 218 DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 219 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 220 DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 221 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 222}; 223 224static const struct samsung_clk_group top_cmu_clks[] = { 225 /* CMU_TOP_PURECLKCOMP */ 226 { S_CLK_PLL, top_pure_pll_clks, ARRAY_SIZE(top_pure_pll_clks) }, 227 { S_CLK_MUX, top_pure_mux_clks, ARRAY_SIZE(top_pure_mux_clks) }, 228 { S_CLK_DIV, top_pure_div_clks, ARRAY_SIZE(top_pure_div_clks) }, 229 230 /* CMU_TOP clocks for CMU_CORE */ 231 { S_CLK_MUX, top_core_mux_clks, ARRAY_SIZE(top_core_mux_clks) }, 232 { S_CLK_GATE, top_core_gate_clks, ARRAY_SIZE(top_core_gate_clks) }, 233 { S_CLK_DIV, top_core_div_clks, ARRAY_SIZE(top_core_div_clks) }, 234 235 /* CMU_TOP clocks for CMU_HSI */ 236 { S_CLK_MUX, top_hsi_mux_clks, ARRAY_SIZE(top_hsi_mux_clks) }, 237 { S_CLK_GATE, top_hsi_gate_clks, ARRAY_SIZE(top_hsi_gate_clks) }, 238 { S_CLK_DIV, top_hsi_div_clks, ARRAY_SIZE(top_hsi_div_clks) }, 239 240 /* CMU_TOP clocks for CMU_PERI */ 241 { S_CLK_MUX, top_peri_mux_clks, ARRAY_SIZE(top_peri_mux_clks) }, 242 { S_CLK_GATE, top_peri_gate_clks, ARRAY_SIZE(top_peri_gate_clks) }, 243 { S_CLK_DIV, top_peri_div_clks, ARRAY_SIZE(top_peri_div_clks) }, 244}; 245 246static int exynos850_cmu_top_probe(struct udevice *dev) 247{ 248 return samsung_cmu_register_one(dev, CMU_TOP, top_cmu_clks, 249 ARRAY_SIZE(top_cmu_clks)); 250} 251 252static const struct udevice_id exynos850_cmu_top_ids[] = { 253 { .compatible = "samsung,exynos850-cmu-top" }, 254 { } 255}; 256 257SAMSUNG_CLK_OPS(exynos850_cmu_top, CMU_TOP); 258 259U_BOOT_DRIVER(exynos850_cmu_top) = { 260 .name = "exynos850-cmu-top", 261 .id = UCLASS_CLK, 262 .of_match = exynos850_cmu_top_ids, 263 .ops = &exynos850_cmu_top_clk_ops, 264 .probe = exynos850_cmu_top_probe, 265 .flags = DM_FLAG_PRE_RELOC, 266}; 267 268/* ---- CMU_PERI ------------------------------------------------------------ */ 269 270/* Register Offset definitions for CMU_PERI (0x10030000) */ 271#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 272#define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 273#define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 274#define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 275 276/* List of parent clocks for Muxes in CMU_PERI */ 277PNAME(mout_peri_bus_user_p) = { "clock-oscclk", "dout_peri_bus" }; 278PNAME(mout_peri_uart_user_p) = { "clock-oscclk", "dout_peri_uart" }; 279 280static const struct samsung_mux_clock peri_mux_clks[] = { 281 MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 282 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 283 MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 284 mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 285}; 286 287static const struct samsung_gate_clock peri_gate_clks[] = { 288 GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 289 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 290 GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 291 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 292}; 293 294static const struct samsung_clk_group peri_cmu_clks[] = { 295 { S_CLK_MUX, peri_mux_clks, ARRAY_SIZE(peri_mux_clks) }, 296 { S_CLK_GATE, peri_gate_clks, ARRAY_SIZE(peri_gate_clks) }, 297}; 298 299static int exynos850_cmu_peri_probe(struct udevice *dev) 300{ 301 return samsung_register_cmu(dev, CMU_PERI, peri_cmu_clks, 302 exynos850_cmu_top); 303} 304 305static const struct udevice_id exynos850_cmu_peri_ids[] = { 306 { .compatible = "samsung,exynos850-cmu-peri" }, 307 { } 308}; 309 310SAMSUNG_CLK_OPS(exynos850_cmu_peri, CMU_PERI); 311 312U_BOOT_DRIVER(exynos850_cmu_peri) = { 313 .name = "exynos850-cmu-peri", 314 .id = UCLASS_CLK, 315 .of_match = exynos850_cmu_peri_ids, 316 .ops = &exynos850_cmu_peri_clk_ops, 317 .probe = exynos850_cmu_peri_probe, 318 .flags = DM_FLAG_PRE_RELOC, 319}; 320 321/* ---- CMU_CORE ------------------------------------------------------------ */ 322 323/* Register Offset definitions for CMU_CORE (0x12000000) */ 324#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 325#define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 326#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 327#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 328#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 329 330/* List of parent clocks for Muxes in CMU_CORE */ 331PNAME(mout_core_bus_user_p) = { "clock-oscclk", "dout_core_bus" }; 332PNAME(mout_core_mmc_embd_user_p) = { "clock-oscclk", 333 "dout_core_mmc_embd" }; 334 335static const struct samsung_mux_clock core_mux_clks[] = { 336 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 337 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 338 MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 339 mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 340 4, 1, CLK_SET_RATE_PARENT, 0), 341}; 342 343static const struct samsung_div_clock core_div_clks[] = { 344 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 345 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 346}; 347 348static const struct samsung_gate_clock core_gate_clks[] = { 349 GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 350 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 351 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 352 "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 353 21, CLK_SET_RATE_PARENT, 0), 354}; 355 356static const struct samsung_clk_group core_cmu_clks[] = { 357 { S_CLK_MUX, core_mux_clks, ARRAY_SIZE(core_mux_clks) }, 358 { S_CLK_DIV, core_div_clks, ARRAY_SIZE(core_div_clks) }, 359 { S_CLK_GATE, core_gate_clks, ARRAY_SIZE(core_gate_clks) }, 360}; 361 362static int exynos850_cmu_core_probe(struct udevice *dev) 363{ 364 return samsung_register_cmu(dev, CMU_CORE, core_cmu_clks, 365 exynos850_cmu_top); 366} 367 368static const struct udevice_id exynos850_cmu_core_ids[] = { 369 { .compatible = "samsung,exynos850-cmu-core" }, 370 { } 371}; 372 373SAMSUNG_CLK_OPS(exynos850_cmu_core, CMU_CORE); 374 375U_BOOT_DRIVER(exynos850_cmu_core) = { 376 .name = "exynos850-cmu-core", 377 .id = UCLASS_CLK, 378 .of_match = exynos850_cmu_core_ids, 379 .ops = &exynos850_cmu_core_clk_ops, 380 .probe = exynos850_cmu_core_probe, 381 .flags = DM_FLAG_PRE_RELOC, 382}; 383 384/* ---- CMU_HSI ------------------------------------------------------------- */ 385 386/* Register Offset definitions for CMU_HSI (0x13400000) */ 387#define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 388#define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 389#define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 390#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 391#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 392#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 393#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 394#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 395#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 396 397/* List of parent clocks for Muxes in CMU_HSI */ 398PNAME(mout_hsi_bus_user_p) = { "clock-oscclk", "dout_hsi_bus" }; 399PNAME(mout_hsi_mmc_card_user_p) = { "clock-oscclk", "dout_hsi_mmc_card" }; 400PNAME(mout_hsi_usb20drd_user_p) = { "clock-oscclk", "dout_hsi_usb20drd" }; 401 402static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 403 MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 404 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 405 MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 406 mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 407 4, 1, CLK_SET_RATE_PARENT, 0), 408 MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 409 mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 410 4, 1), 411}; 412 413static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 414 GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 415 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 416 GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "clock-oscclk", 417 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 418 GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 419 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 420 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 421 "mout_hsi_mmc_card_user", 422 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 423 GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 424 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 425 GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 426 "mout_hsi_bus_user", 427 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 428}; 429 430static const struct samsung_clk_group hsi_cmu_clks[] = { 431 { S_CLK_MUX, hsi_mux_clks, ARRAY_SIZE(hsi_mux_clks) }, 432 { S_CLK_GATE, hsi_gate_clks, ARRAY_SIZE(hsi_gate_clks) }, 433}; 434 435static int exynos850_cmu_hsi_probe(struct udevice *dev) 436{ 437 return samsung_register_cmu(dev, CMU_HSI, hsi_cmu_clks, 438 exynos850_cmu_hsi); 439} 440 441static const struct udevice_id exynos850_cmu_hsi_ids[] = { 442 { .compatible = "samsung,exynos850-cmu-hsi" }, 443 { } 444}; 445 446SAMSUNG_CLK_OPS(exynos850_cmu_hsi, CMU_HSI); 447 448U_BOOT_DRIVER(exynos850_cmu_hsi) = { 449 .name = "exynos850-cmu-hsi", 450 .id = UCLASS_CLK, 451 .of_match = exynos850_cmu_hsi_ids, 452 .ops = &exynos850_cmu_hsi_clk_ops, 453 .probe = exynos850_cmu_hsi_probe, 454 .flags = DM_FLAG_PRE_RELOC, 455}; 456