1U-Boot for Freescale i.MX6 2 3This file contains information for the port of U-Boot to the Freescale i.MX6 4SoC. 5 61. CONVENTIONS FOR FUSE ASSIGNMENTS 7----------------------------------- 8 91.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the 10 16 msbs in word 3[15:0]. 11 For i.MX6SX and i.MX6UL, they have two MAC addresses. The second MAC address 12 is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in 13 word 4. 14 15Example: 16 17For reading the MAC address fuses on a MX6Q: 18 19- The MAC address is stored in two fuse addresses (the fuse addresses are 20described in the Fusemap Descriptions table from the mx6q Reference Manual): 21 220x620[31:0] - MAC_ADDR[31:0] 230x630[15:0] - MAC_ADDR[47:32] 24 25In order to use the fuse API, we need to pass the bank and word values, which 26are calculated as below: 27 28Fuse address for the lower MAC address: 0x620 29Base address for the fuses: 0x400 30 31(0x620 - 0x400)/0x10 = 0x22 = 34 decimal 32 33As the fuses are arranged in banks of 8 words: 34 3534 / 8 = 4 and the remainder is 2, so in this case: 36 37bank = 4 38word = 2 39 40And the U-Boot command would be: 41 42=> fuse read 4 2 43Reading bank 4: 44 45Word 0x00000002: 9f027772 46 47Doing the same for the upper MAC address: 48 49Fuse address for the upper MAC address: 0x630 50Base address for the fuses: 0x400 51 52(0x630 - 0x400)/0x10 = 0x23 = 35 decimal 53 54As the fuses are arranged in banks of 8 words: 55 5635 / 8 = 4 and the remainder is 3, so in this case: 57 58bank = 4 59word = 3 60 61And the U-Boot command would be: 62 63=> fuse read 4 3 64Reading bank 4: 65 66Word 0x00000003: 00000004 67 68,which matches the ethaddr value: 69=> echo ${ethaddr} 7000:04:9f:02:77:72 71 72Some other useful hints: 73 74- The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference 75Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register 76Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual, 77Rev. 1, 04/2013" document. For example, for the MAC fuses we have: 78 79Address: 8021B_C620 Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0) 81 8221B_C630 Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1) 83 84- The command '=> fuse read 4 2 2' reads the whole MAC addresses at once: 85 86=> fuse read 4 2 2 87Reading bank 4: 88 89Word 0x00000002: 9f027772 00000004 90 91NAND Boot on i.MX6 with SPL support 92-------------------------------------- 93 94Writing/updating boot image in nand device is not straight forward in 95i.MX6 platform and it requires boot control block(BCB) to be configured. 96 97BCB contains two data structures, Firmware Configuration Block(FCB) and 98Discovered Bad Block Table(DBBT). FCB has nand timings, DBBT search area, 99and firmware. See IMX6DQRM Section 8.5.2.2 100for more information. 101 102We can't use 'nand write' command to write SPL/firmware image directly 103like other platforms does. So we need special setup to write BCB block 104as per IMX6QDL reference manual 'nandbcb update' command do that job. 105 106for nand boot, up on reset bootrom look for FCB structure in 107first block's if FCB found the nand timings are loaded for 108further reads. once FCB read done, DTTB will be loaded and 109finally firmware will be loaded which is boot image. 110 111cmd_nandbcb will create FCB these structures 112by taking mtd partition as an example. 113- initial code will erase entire partition 114- followed by FCB setup, like first 2 blocks for FCB/DBBT write, 115 and next block for FW1/SPL 116- write firmware at FW1 block and 117- finally write fcb/dttb in first 2 block. 118 119Typical NAND BCB layout: 120======================= 121 122 no.of blocks = partition size / erasesize 123 no.of fcb/dbbt blocks = 2 124 FW1 offset = no.of fcb/dbbt 125 126block 0 1 2 127 ------------------------------- 128 |FCB/DBBT 0|FCB/DBBT 1| FW 1 | 129 -------------------------------- 130 131On summary, nandbcb update will 132- erase the entire partition 133- create BCB by creating 2 FCB/BDDT block followed by 134 1 FW blocks based on partition size and erasesize. 135- fill FCB/DBBT structures 136- write FW/SPL in FW1 137- write FCB/DBBT in first 2 blocks 138 139step-1: write SPL 140 141icorem6qdl> ext4load mmc 0:1 $loadaddr SPL 14239936 bytes read in 10 ms (3.8 MiB/s) 143 144icorem6qdl> nandbcb update $loadaddr spl $filesize 145device 0 offset 0x0, size 0x9c00 146Erasing at 0x1c0000 -- 100% complete. 147NAND fw write: 0x80000 offset, 0xb000 bytes written: OK 148 149step-2: write u-boot-dtb.img 150 151icorem6qdl> nand erase.part uboot 152 153NAND erase.part: device 0 offset 0x200000, size 0x200000 154Erasing at 0x3c0000 -- 100% complete. 155OK 156 157icorem6qdl> ext4load mmc 0:1 $loadaddr u-boot-dtb.img 158589094 bytes read in 37 ms (15.2 MiB/s) 159 160icorem6qdl> nand write ${loadaddr} uboot ${filesize} 161 162NAND write: device 0 offset 0x200000, size 0x8fd26 163 589094 bytes written: OK 164icorem6qdl> 165 166SPL Stack size and location notes 167--------------------------------- 168 169If we have CONFIG_MX6_OCRAM_256KB then see Figure 8.4.1 in IMX6DQ Reference 170manuals: 171 - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF 172 - BOOT ROM stack is at 0x0093FFB8 173 - if icache/dcache is enabled (eFuse/strapping controlled) then the 174 IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to 175 fit between 0x00907000 and 0x00938000. 176 - Additionally the BOOT ROM loads what they consider the firmware image 177 which consists of a 4K header in front of us that contains the IVT, DCD 178 and some padding thus 'our' max size is really 0x00908000 - 0x00938000 179 or 192KB 180 - Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the 181 SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a 182 boot media (given that boot media specific offset is configured properly). 183and if we don't, see Figure 8-3 in IMX6SDL Reference manuals: 184 - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF 185 - BOOT ROM stack is at 0x0091FFB8 186 - if icache/dcache is enabled (eFuse/strapping controlled) then the 187 IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to 188 fit between 0x00907000 and 0x00918000. 189 - Additionally the BOOT ROM loads what they consider the firmware image 190 which consists of a 4K header in front of us that contains the IVT, DCD 191 and some padding thus 'our' max size is really 0x00908000 - 0x00918000 192 or 64KB 193 - Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the 194 SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a 195 boot media (given that boot media specific offset is configured properly). 196