1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@amd.com> 5 */ 6 7#include <common.h> 8#include <command.h> 9#include <cpu_func.h> 10#include <debug_uart.h> 11#include <dfu.h> 12#include <env.h> 13#include <env_internal.h> 14#include <init.h> 15#include <log.h> 16#include <net.h> 17#include <sata.h> 18#include <ahci.h> 19#include <scsi.h> 20#include <soc.h> 21#include <spl.h> 22#include <malloc.h> 23#include <memalign.h> 24#include <wdt.h> 25#include <asm/arch/clk.h> 26#include <asm/arch/hardware.h> 27#include <asm/arch/sys_proto.h> 28#include <asm/arch/psu_init_gpl.h> 29#include <asm/cache.h> 30#include <asm/global_data.h> 31#include <asm/io.h> 32#include <asm/ptrace.h> 33#include <dm/device.h> 34#include <dm/uclass.h> 35#include <usb.h> 36#include <dwc3-uboot.h> 37#include <zynqmppl.h> 38#include <zynqmp_firmware.h> 39#include <g_dnl.h> 40#include <linux/bitops.h> 41#include <linux/delay.h> 42#include <linux/sizes.h> 43#include "../common/board.h" 44 45#include "pm_cfg_obj.h" 46 47DECLARE_GLOBAL_DATA_PTR; 48 49#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) 50static xilinx_desc zynqmppl = { 51 xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, NULL, 52 ZYNQMP_FPGA_FLAGS 53}; 54#endif 55 56int __maybe_unused psu_uboot_init(void) 57{ 58 int ret; 59 60 ret = psu_init(); 61 if (ret) 62 return ret; 63 64 /* 65 * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon 66 * supply sense channel to SysMon supply registers inside the IP. 67 * This register must be programmed to complete SysMon IP 68 * configuration. The default register configuration after 69 * power-up is incorrect. Hence, fix this by writing the 70 * correct value - 0x3210. 71 */ 72 writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL, 73 ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS); 74 75 /* Delay is required for clocks to be propagated */ 76 udelay(1000000); 77 78 return 0; 79} 80 81#if !defined(CONFIG_SPL_BUILD) 82# if defined(CONFIG_DEBUG_UART_BOARD_INIT) 83void board_debug_uart_init(void) 84{ 85# if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) 86 psu_uboot_init(); 87# endif 88} 89# endif 90 91# if defined(CONFIG_BOARD_EARLY_INIT_F) 92int board_early_init_f(void) 93{ 94 int ret = 0; 95# if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) && !defined(CONFIG_DEBUG_UART_BOARD_INIT) 96 ret = psu_uboot_init(); 97# endif 98 return ret; 99} 100# endif 101#endif 102 103static int multi_boot(void) 104{ 105 u32 multiboot = 0; 106 int ret; 107 108 ret = zynqmp_mmio_read((ulong)&csu_base->multi_boot, &multiboot); 109 if (ret) 110 return -EINVAL; 111 112 return multiboot; 113} 114 115#if defined(CONFIG_SPL_BUILD) 116static void restore_jtag(void) 117{ 118 if (current_el() != 3) 119 return; 120 121 writel(CSU_JTAG_SEC_GATE_DISABLE, &csu_base->jtag_sec); 122 writel(CSU_JTAG_DAP_ENABLE_DEBUG, &csu_base->jtag_dap_cfg); 123 writel(CSU_JTAG_CHAIN_WR_SETUP, &csu_base->jtag_chain_status_wr); 124 writel(CRLAPB_DBG_LPD_CTRL_SETUP_CLK, &crlapb_base->dbg_lpd_ctrl); 125 writel(CRLAPB_RST_LPD_DBG_RESET, &crlapb_base->rst_lpd_dbg); 126 writel(CSU_PCAP_PROG_RELEASE_PL, &csu_base->pcap_prog); 127} 128#endif 129 130static void print_secure_boot(void) 131{ 132 u32 status = 0; 133 134 if (zynqmp_mmio_read((ulong)&csu_base->status, &status)) 135 return; 136 137 printf("Secure Boot:\t%sauthenticated, %sencrypted\n", 138 status & ZYNQMP_CSU_STATUS_AUTHENTICATED ? "" : "not ", 139 status & ZYNQMP_CSU_STATUS_ENCRYPTED ? "" : "not "); 140} 141 142int board_init(void) 143{ 144#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) 145 struct udevice *soc; 146 char name[SOC_MAX_STR_SIZE]; 147 int ret; 148#endif 149 150#if defined(CONFIG_SPL_BUILD) 151 /* Check *at build time* if the filename is an non-empty string */ 152 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) 153 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, 154 zynqmp_pm_cfg_obj_size); 155#endif 156 157#if defined(CONFIG_ZYNQMP_FIRMWARE) 158 struct udevice *dev; 159 160 uclass_get_device_by_name(UCLASS_FIRMWARE, "power-management", &dev); 161 if (!dev) { 162 uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev); 163 if (!dev) 164 panic("PMU Firmware device not found - Enable it"); 165 } 166#endif 167 168#if defined(CONFIG_SPL_BUILD) 169 printf("Silicon version:\t%d\n", zynqmp_get_silicon_version()); 170 171 /* the CSU disables the JTAG interface when secure boot is enabled */ 172 if (CONFIG_IS_ENABLED(ZYNQMP_RESTORE_JTAG)) 173 restore_jtag(); 174#else 175 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) 176 xilinx_read_eeprom(); 177#endif 178 179 printf("EL Level:\tEL%d\n", current_el()); 180 181#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) 182 ret = soc_get(&soc); 183 if (!ret) { 184 ret = soc_get_machine(soc, name, sizeof(name)); 185 if (ret >= 0) { 186 zynqmppl.name = strdup(name); 187 fpga_init(); 188 fpga_add(fpga_xilinx, &zynqmppl); 189 } 190 } 191#endif 192 193 /* display secure boot information */ 194 print_secure_boot(); 195 if (current_el() == 3) 196 printf("Multiboot:\t%d\n", multi_boot()); 197 198 return 0; 199} 200 201int board_early_init_r(void) 202{ 203 u32 val; 204 205 if (current_el() != 3) 206 return 0; 207 208 val = readl(&crlapb_base->timestamp_ref_ctrl); 209 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 210 211 if (!val) { 212 val = readl(&crlapb_base->timestamp_ref_ctrl); 213 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 214 writel(val, &crlapb_base->timestamp_ref_ctrl); 215 216 /* Program freq register in System counter */ 217 writel(zynqmp_get_system_timer_freq(), 218 &iou_scntr_secure->base_frequency_id_register); 219 /* And enable system counter */ 220 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 221 &iou_scntr_secure->counter_control_register); 222 } 223 return 0; 224} 225 226unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, 227 char *const argv[]) 228{ 229 int ret = 0; 230 231 if (current_el() > 1) { 232 smp_kick_all_cpus(); 233 dcache_disable(); 234 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry, 235 ES_TO_AARCH64); 236 } else { 237 printf("FAIL: current EL is not above EL1\n"); 238 ret = EINVAL; 239 } 240 return ret; 241} 242 243#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE) 244int dram_init_banksize(void) 245{ 246 int ret; 247 248 ret = fdtdec_setup_memory_banksize(); 249 if (ret) 250 return ret; 251 252 mem_map_fill(); 253 254 return 0; 255} 256 257int dram_init(void) 258{ 259 if (fdtdec_setup_mem_size_base() != 0) 260 return -EINVAL; 261 262 return 0; 263} 264 265#else 266int dram_init_banksize(void) 267{ 268 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; 269 gd->bd->bi_dram[0].size = get_effective_memsize(); 270 271 mem_map_fill(); 272 273 return 0; 274} 275 276int dram_init(void) 277{ 278 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 279 CFG_SYS_SDRAM_SIZE); 280 281 return 0; 282} 283#endif 284 285#if !CONFIG_IS_ENABLED(SYSRESET) 286void reset_cpu(void) 287{ 288} 289#endif 290 291static u8 __maybe_unused zynqmp_get_bootmode(void) 292{ 293 u8 bootmode; 294 u32 reg = 0; 295 int ret; 296 297 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®); 298 if (ret) 299 return -EINVAL; 300 301 debug("HW boot mode: %x\n", reg & BOOT_MODES_MASK); 302 debug("ALT boot mode: %x\n", reg >> BOOT_MODE_ALT_SHIFT); 303 304 if (reg >> BOOT_MODE_ALT_SHIFT) 305 reg >>= BOOT_MODE_ALT_SHIFT; 306 307 bootmode = reg & BOOT_MODES_MASK; 308 309 return bootmode; 310} 311 312#if defined(CONFIG_BOARD_LATE_INIT) 313static const struct { 314 u32 bit; 315 const char *name; 316} reset_reasons[] = { 317 { RESET_REASON_DEBUG_SYS, "DEBUG" }, 318 { RESET_REASON_SOFT, "SOFT" }, 319 { RESET_REASON_SRST, "SRST" }, 320 { RESET_REASON_PSONLY, "PS-ONLY" }, 321 { RESET_REASON_PMU, "PMU" }, 322 { RESET_REASON_INTERNAL, "INTERNAL" }, 323 { RESET_REASON_EXTERNAL, "EXTERNAL" }, 324 {} 325}; 326 327static int reset_reason(void) 328{ 329 u32 reg; 330 int i, ret; 331 const char *reason = NULL; 332 333 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®); 334 if (ret) 335 return -EINVAL; 336 337 puts("Reset reason:\t"); 338 339 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) { 340 if (reg & reset_reasons[i].bit) { 341 reason = reset_reasons[i].name; 342 printf("%s ", reset_reasons[i].name); 343 break; 344 } 345 } 346 347 puts("\n"); 348 349 env_set("reset_reason", reason); 350 351 return 0; 352} 353 354static int set_fdtfile(void) 355{ 356 char *compatible, *fdtfile; 357 const char *suffix = ".dtb"; 358 const char *vendor = "xilinx/"; 359 int fdt_compat_len; 360 361 if (env_get("fdtfile")) 362 return 0; 363 364 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", 365 &fdt_compat_len); 366 if (compatible && fdt_compat_len) { 367 char *name; 368 369 debug("Compatible: %s\n", compatible); 370 371 name = strchr(compatible, ','); 372 if (!name) 373 return -EINVAL; 374 375 name++; 376 377 fdtfile = calloc(1, strlen(vendor) + strlen(name) + 378 strlen(suffix) + 1); 379 if (!fdtfile) 380 return -ENOMEM; 381 382 sprintf(fdtfile, "%s%s%s", vendor, name, suffix); 383 384 env_set("fdtfile", fdtfile); 385 free(fdtfile); 386 } 387 388 return 0; 389} 390 391static int boot_targets_setup(void) 392{ 393 u8 bootmode; 394 struct udevice *dev; 395 int bootseq = -1; 396 int bootseq_len = 0; 397 int env_targets_len = 0; 398 const char *mode = NULL; 399 char *new_targets; 400 char *env_targets; 401 402 bootmode = zynqmp_get_bootmode(); 403 404 puts("Bootmode: "); 405 switch (bootmode) { 406 case USB_MODE: 407 puts("USB_MODE\n"); 408 mode = "usb_dfu0 usb_dfu1"; 409 env_set("modeboot", "usb_dfu_spl"); 410 break; 411 case JTAG_MODE: 412 puts("JTAG_MODE\n"); 413 mode = "jtag pxe dhcp"; 414 env_set("modeboot", "jtagboot"); 415 break; 416 case QSPI_MODE_24BIT: 417 case QSPI_MODE_32BIT: 418 mode = "qspi0"; 419 puts("QSPI_MODE\n"); 420 env_set("modeboot", "qspiboot"); 421 break; 422 case EMMC_MODE: 423 puts("EMMC_MODE\n"); 424 if (uclass_get_device_by_name(UCLASS_MMC, 425 "mmc@ff160000", &dev) && 426 uclass_get_device_by_name(UCLASS_MMC, 427 "sdhci@ff160000", &dev)) { 428 debug("SD0 driver for SD0 device is not present\n"); 429 break; 430 } 431 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev)); 432 433 mode = "mmc"; 434 bootseq = dev_seq(dev); 435 env_set("modeboot", "emmcboot"); 436 break; 437 case SD_MODE: 438 puts("SD_MODE\n"); 439 if (uclass_get_device_by_name(UCLASS_MMC, 440 "mmc@ff160000", &dev) && 441 uclass_get_device_by_name(UCLASS_MMC, 442 "sdhci@ff160000", &dev)) { 443 debug("SD0 driver for SD0 device is not present\n"); 444 break; 445 } 446 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev)); 447 448 mode = "mmc"; 449 bootseq = dev_seq(dev); 450 env_set("modeboot", "sdboot"); 451 break; 452 case SD1_LSHFT_MODE: 453 puts("LVL_SHFT_"); 454 fallthrough; 455 case SD_MODE1: 456 puts("SD_MODE1\n"); 457 if (uclass_get_device_by_name(UCLASS_MMC, 458 "mmc@ff170000", &dev) && 459 uclass_get_device_by_name(UCLASS_MMC, 460 "sdhci@ff170000", &dev)) { 461 debug("SD1 driver for SD1 device is not present\n"); 462 break; 463 } 464 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev)); 465 466 mode = "mmc"; 467 bootseq = dev_seq(dev); 468 env_set("modeboot", "sdboot"); 469 break; 470 case NAND_MODE: 471 puts("NAND_MODE\n"); 472 mode = "nand0"; 473 env_set("modeboot", "nandboot"); 474 break; 475 default: 476 printf("Invalid Boot Mode:0x%x\n", bootmode); 477 break; 478 } 479 480 if (mode) { 481 if (bootseq >= 0) { 482 bootseq_len = snprintf(NULL, 0, "%i", bootseq); 483 debug("Bootseq len: %x\n", bootseq_len); 484 env_set_hex("bootseq", bootseq); 485 } 486 487 /* 488 * One terminating char + one byte for space between mode 489 * and default boot_targets 490 */ 491 env_targets = env_get("boot_targets"); 492 if (env_targets) 493 env_targets_len = strlen(env_targets); 494 495 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 + 496 bootseq_len); 497 if (!new_targets) 498 return -ENOMEM; 499 500 if (bootseq >= 0) 501 sprintf(new_targets, "%s%x %s", mode, bootseq, 502 env_targets ? env_targets : ""); 503 else 504 sprintf(new_targets, "%s %s", mode, 505 env_targets ? env_targets : ""); 506 507 env_set("boot_targets", new_targets); 508 free(new_targets); 509 } 510 511 return 0; 512} 513 514int board_late_init(void) 515{ 516 int ret, multiboot; 517 518#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD) 519 usb_ether_init(); 520#endif 521 522 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { 523 debug("Saved variables - Skipping\n"); 524 return 0; 525 } 526 527 if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) 528 return 0; 529 530 ret = set_fdtfile(); 531 if (ret) 532 return ret; 533 534 multiboot = multi_boot(); 535 if (multiboot >= 0) 536 env_set_hex("multiboot", multiboot); 537 538 if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) { 539 ret = boot_targets_setup(); 540 if (ret) 541 return ret; 542 } 543 544 reset_reason(); 545 546 return board_late_init_xilinx(); 547} 548#endif 549 550int checkboard(void) 551{ 552 puts("Board: Xilinx ZynqMP\n"); 553 return 0; 554} 555 556int mmc_get_env_dev(void) 557{ 558 struct udevice *dev; 559 int bootseq = 0; 560 561 switch (zynqmp_get_bootmode()) { 562 case EMMC_MODE: 563 case SD_MODE: 564 if (uclass_get_device_by_name(UCLASS_MMC, 565 "mmc@ff160000", &dev) && 566 uclass_get_device_by_name(UCLASS_MMC, 567 "sdhci@ff160000", &dev)) { 568 return -1; 569 } 570 bootseq = dev_seq(dev); 571 break; 572 case SD1_LSHFT_MODE: 573 case SD_MODE1: 574 if (uclass_get_device_by_name(UCLASS_MMC, 575 "mmc@ff170000", &dev) && 576 uclass_get_device_by_name(UCLASS_MMC, 577 "sdhci@ff170000", &dev)) { 578 return -1; 579 } 580 bootseq = dev_seq(dev); 581 break; 582 default: 583 break; 584 } 585 586 debug("bootseq %d\n", bootseq); 587 588 return bootseq; 589} 590 591#if defined(CONFIG_ENV_IS_NOWHERE) 592enum env_location env_get_location(enum env_operation op, int prio) 593{ 594 u32 bootmode = zynqmp_get_bootmode(); 595 596 if (prio) 597 return ENVL_UNKNOWN; 598 599 switch (bootmode) { 600 case EMMC_MODE: 601 case SD_MODE: 602 case SD1_LSHFT_MODE: 603 case SD_MODE1: 604 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT)) 605 return ENVL_FAT; 606 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)) 607 return ENVL_EXT4; 608 return ENVL_NOWHERE; 609 case NAND_MODE: 610 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND)) 611 return ENVL_NAND; 612 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI)) 613 return ENVL_UBI; 614 return ENVL_NOWHERE; 615 case QSPI_MODE_24BIT: 616 case QSPI_MODE_32BIT: 617 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) 618 return ENVL_SPI_FLASH; 619 return ENVL_NOWHERE; 620 case JTAG_MODE: 621 default: 622 return ENVL_NOWHERE; 623 } 624} 625#endif 626 627#if defined(CONFIG_SET_DFU_ALT_INFO) 628 629#define DFU_ALT_BUF_LEN SZ_1K 630 631static void mtd_found_part(u32 *base, u32 *size) 632{ 633 struct mtd_info *part, *mtd; 634 635 mtd_probe_devices(); 636 637 mtd = get_mtd_device_nm("nor0"); 638 if (!IS_ERR_OR_NULL(mtd)) { 639 list_for_each_entry(part, &mtd->partitions, node) { 640 debug("0x%012llx-0x%012llx : \"%s\"\n", 641 part->offset, part->offset + part->size, 642 part->name); 643 644 if (*base >= part->offset && 645 *base < part->offset + part->size) { 646 debug("Found my partition: %d/%s\n", 647 part->index, part->name); 648 *base = part->offset; 649 *size = part->size; 650 break; 651 } 652 } 653 } 654} 655 656void set_dfu_alt_info(char *interface, char *devstr) 657{ 658 int multiboot, bootseq = 0, len = 0; 659 660 ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); 661 662 if (env_get("dfu_alt_info")) 663 return; 664 665 memset(buf, 0, sizeof(buf)); 666 667 multiboot = multi_boot(); 668 if (multiboot < 0) 669 multiboot = 0; 670 671 multiboot = env_get_hex("multiboot", multiboot); 672 debug("Multiboot: %d\n", multiboot); 673 674 switch (zynqmp_get_bootmode()) { 675 case EMMC_MODE: 676 case SD_MODE: 677 case SD1_LSHFT_MODE: 678 case SD_MODE1: 679 bootseq = mmc_get_env_dev(); 680 681 len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot", 682 bootseq); 683 684 if (multiboot) 685 len += snprintf(buf + len, DFU_ALT_BUF_LEN, 686 "%04d", multiboot); 687 688 len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1", 689 bootseq); 690#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) 691 if (strlen(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)) 692 len += snprintf(buf + len, DFU_ALT_BUF_LEN, 693 ";%s fat %d 1", 694 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, 695 bootseq); 696#endif 697 break; 698 case QSPI_MODE_24BIT: 699 case QSPI_MODE_32BIT: 700 { 701 u32 base = multiboot * SZ_32K; 702 u32 size = 0x1500000; 703 u32 limit = size; 704 705 mtd_found_part(&base, &limit); 706 707#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) 708 size = limit; 709 limit = CONFIG_SYS_SPI_U_BOOT_OFFS; 710#endif 711 712 len += snprintf(buf + len, DFU_ALT_BUF_LEN, 713 "sf 0:0=boot.bin raw 0x%x 0x%x", 714 base, limit); 715#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) && defined(CONFIG_SYS_SPI_U_BOOT_OFFS) 716 if (strlen(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)) 717 len += snprintf(buf + len, DFU_ALT_BUF_LEN, 718 ";%s raw 0x%x 0x%x", 719 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, 720 base + limit, size - limit); 721#endif 722 } 723 break; 724 default: 725 return; 726 } 727 728 env_set("dfu_alt_info", buf); 729 puts("DFU alt info setting: done\n"); 730} 731#endif 732 733#if defined(CONFIG_SPL_SPI_LOAD) 734unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) 735{ 736 u32 offset; 737 int multiboot = multi_boot(); 738 739 offset = multiboot * SZ_32K; 740 offset += CONFIG_SYS_SPI_U_BOOT_OFFS; 741 742 log_info("SPI offset:\t0x%x\n", offset); 743 744 return offset; 745} 746#endif 747