1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2013 Freescale Semiconductor, Inc. 4 * Copyright (C) 2014 O.S. Systems Software LTDA. 5 * 6 * Author: Fabio Estevam <fabio.estevam@freescale.com> 7 */ 8 9#include <common.h> 10#include <image.h> 11#include <init.h> 12#include <log.h> 13#include <asm/arch/clock.h> 14#include <asm/arch/crm_regs.h> 15#include <asm/arch/iomux.h> 16#include <asm/arch/imx-regs.h> 17#include <asm/arch/mx6-pins.h> 18#include <asm/arch/mxc_hdmi.h> 19#include <asm/arch/sys_proto.h> 20#include <asm/global_data.h> 21#include <asm/gpio.h> 22#include <asm/mach-imx/iomux-v3.h> 23#include <asm/mach-imx/mxc_i2c.h> 24#include <asm/mach-imx/boot_mode.h> 25#include <asm/mach-imx/video.h> 26#include <asm/mach-imx/sata.h> 27#include <asm/io.h> 28#include <env.h> 29#include <linux/delay.h> 30#include <linux/sizes.h> 31#include <miiphy.h> 32#include <netdev.h> 33#include <phy.h> 34#include <i2c.h> 35#include <power/pmic.h> 36#include <power/pfuze100_pmic.h> 37 38DECLARE_GLOBAL_DATA_PTR; 39 40#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 42 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 43 44#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 46 47#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 49 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 50 51#define ETH_PHY_RESET IMX_GPIO_NR(3, 29) 52#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13) 53#define REV_DETECTION IMX_GPIO_NR(2, 28) 54 55/* Speed defined in Kconfig is only applicable when not using DM_I2C. */ 56#if CONFIG_IS_ENABLED(DM_I2C) 57#define I2C1_SPEED_NON_DM 0 58#define I2C2_SPEED_NON_DM 0 59#else 60#define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED 61#define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED 62#endif 63 64static bool with_pmic; 65 66int dram_init(void) 67{ 68 gd->ram_size = imx_ddr_size(); 69 70 return 0; 71} 72 73static iomux_v3_cfg_t const uart1_pads[] = { 74 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 75 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 76}; 77 78static iomux_v3_cfg_t const enet_pads[] = { 79 /* AR8031 PHY Reset */ 80 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 81}; 82 83static iomux_v3_cfg_t const enet_ar8035_power_pads[] = { 84 /* AR8035 POWER */ 85 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)), 86}; 87 88static iomux_v3_cfg_t const rev_detection_pad[] = { 89 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), 90}; 91 92static void setup_iomux_uart(void) 93{ 94 SETUP_IOMUX_PADS(uart1_pads); 95} 96 97static void setup_iomux_enet(void) 98{ 99 SETUP_IOMUX_PADS(enet_pads); 100 101 if (with_pmic) { 102 SETUP_IOMUX_PADS(enet_ar8035_power_pads); 103 /* enable AR8035 POWER */ 104 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER"); 105 gpio_direction_output(ETH_PHY_AR8035_POWER, 0); 106 } 107 /* wait until 3.3V of PHY and clock become stable */ 108 mdelay(10); 109 110 /* Reset AR8031 PHY */ 111 gpio_request(ETH_PHY_RESET, "PHY_RESET"); 112 gpio_direction_output(ETH_PHY_RESET, 0); 113 mdelay(10); 114 gpio_set_value(ETH_PHY_RESET, 1); 115 udelay(100); 116} 117 118static int ar8031_phy_fixup(struct phy_device *phydev) 119{ 120 unsigned short val; 121 int mask; 122 123 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 124 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 125 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 126 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 127 128 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 129 if (with_pmic) 130 mask = 0xffe7; /* AR8035 */ 131 else 132 mask = 0xffe3; /* AR8031 */ 133 134 val &= mask; 135 val |= 0x18; 136 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 137 138 /* introduce tx clock delay */ 139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 140 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 141 val |= 0x0100; 142 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 143 144 return 0; 145} 146 147int board_phy_config(struct phy_device *phydev) 148{ 149 ar8031_phy_fixup(phydev); 150 151 if (phydev->drv->config) 152 phydev->drv->config(phydev); 153 154 return 0; 155} 156 157#if defined(CONFIG_VIDEO_IPUV3) 158struct i2c_pads_info mx6q_i2c2_pad_info = { 159 .scl = { 160 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL 161 | MUX_PAD_CTRL(I2C_PAD_CTRL), 162 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 163 | MUX_PAD_CTRL(I2C_PAD_CTRL), 164 .gp = IMX_GPIO_NR(4, 12) 165 }, 166 .sda = { 167 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA 168 | MUX_PAD_CTRL(I2C_PAD_CTRL), 169 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 170 | MUX_PAD_CTRL(I2C_PAD_CTRL), 171 .gp = IMX_GPIO_NR(4, 13) 172 } 173}; 174 175struct i2c_pads_info mx6dl_i2c2_pad_info = { 176 .scl = { 177 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL 178 | MUX_PAD_CTRL(I2C_PAD_CTRL), 179 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 180 | MUX_PAD_CTRL(I2C_PAD_CTRL), 181 .gp = IMX_GPIO_NR(4, 12) 182 }, 183 .sda = { 184 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA 185 | MUX_PAD_CTRL(I2C_PAD_CTRL), 186 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 187 | MUX_PAD_CTRL(I2C_PAD_CTRL), 188 .gp = IMX_GPIO_NR(4, 13) 189 } 190}; 191 192struct i2c_pads_info mx6q_i2c3_pad_info = { 193 .scl = { 194 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL 195 | MUX_PAD_CTRL(I2C_PAD_CTRL), 196 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05 197 | MUX_PAD_CTRL(I2C_PAD_CTRL), 198 .gp = IMX_GPIO_NR(1, 5) 199 }, 200 .sda = { 201 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA 202 | MUX_PAD_CTRL(I2C_PAD_CTRL), 203 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11 204 | MUX_PAD_CTRL(I2C_PAD_CTRL), 205 .gp = IMX_GPIO_NR(7, 11) 206 } 207}; 208 209struct i2c_pads_info mx6dl_i2c3_pad_info = { 210 .scl = { 211 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL 212 | MUX_PAD_CTRL(I2C_PAD_CTRL), 213 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05 214 | MUX_PAD_CTRL(I2C_PAD_CTRL), 215 .gp = IMX_GPIO_NR(1, 5) 216 }, 217 .sda = { 218 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA 219 | MUX_PAD_CTRL(I2C_PAD_CTRL), 220 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11 221 | MUX_PAD_CTRL(I2C_PAD_CTRL), 222 .gp = IMX_GPIO_NR(7, 11) 223 } 224}; 225 226static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = { 227 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), 228 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */ 229 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */ 230 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */ 231 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */ 232 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), 233 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), 234 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), 235 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), 236 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), 237 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), 238 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), 239 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), 240 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), 241 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), 242 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), 243 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), 244 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), 245 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), 246 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), 247 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), 248 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), 249 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), 250 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */ 251 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */ 252}; 253 254static void do_enable_hdmi(struct display_info_t const *dev) 255{ 256 imx_enable_hdmi_phy(); 257} 258 259static int detect_i2c(struct display_info_t const *dev) 260{ 261#if CONFIG_IS_ENABLED(DM_I2C) 262 struct udevice *bus, *udev; 263 int rc; 264 265 rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus); 266 if (rc) 267 return rc; 268 rc = dm_i2c_probe(bus, dev->addr, 0, &udev); 269 if (rc) 270 return 0; 271 return 1; 272#else 273 return (0 == i2c_set_bus_num(dev->bus)) && 274 (0 == i2c_probe(dev->addr)); 275#endif 276} 277 278static void enable_fwadapt_7wvga(struct display_info_t const *dev) 279{ 280 SETUP_IOMUX_PADS(fwadapt_7wvga_pads); 281 282 gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN"); 283 gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN"); 284 gpio_direction_output(IMX_GPIO_NR(2, 10), 1); 285 gpio_direction_output(IMX_GPIO_NR(2, 11), 1); 286} 287 288struct display_info_t const displays[] = {{ 289 .bus = -1, 290 .addr = 0, 291 .pixfmt = IPU_PIX_FMT_RGB24, 292 .detect = detect_hdmi, 293 .enable = do_enable_hdmi, 294 .mode = { 295 .name = "HDMI", 296 .refresh = 60, 297 .xres = 1024, 298 .yres = 768, 299 .pixclock = 15385, 300 .left_margin = 220, 301 .right_margin = 40, 302 .upper_margin = 21, 303 .lower_margin = 7, 304 .hsync_len = 60, 305 .vsync_len = 10, 306 .sync = FB_SYNC_EXT, 307 .vmode = FB_VMODE_NONINTERLACED 308} }, { 309 .bus = 1, 310 .addr = 0x10, 311 .pixfmt = IPU_PIX_FMT_RGB666, 312 .detect = detect_i2c, 313 .enable = enable_fwadapt_7wvga, 314 .mode = { 315 .name = "FWBADAPT-LCD-F07A-0102", 316 .refresh = 60, 317 .xres = 800, 318 .yres = 480, 319 .pixclock = 33260, 320 .left_margin = 128, 321 .right_margin = 128, 322 .upper_margin = 22, 323 .lower_margin = 22, 324 .hsync_len = 1, 325 .vsync_len = 1, 326 .sync = 0, 327 .vmode = FB_VMODE_NONINTERLACED 328} } }; 329size_t display_count = ARRAY_SIZE(displays); 330 331static void setup_display(void) 332{ 333 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 334 int reg; 335 336 enable_ipu_clock(); 337 imx_setup_hdmi(); 338 339 reg = readl(&mxc_ccm->chsccdr); 340 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 341 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 342 writel(reg, &mxc_ccm->chsccdr); 343 344 /* Disable LCD backlight */ 345 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20); 346 gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN"); 347 gpio_direction_input(IMX_GPIO_NR(4, 20)); 348} 349#endif /* CONFIG_VIDEO_IPUV3 */ 350 351int board_early_init_f(void) 352{ 353 setup_iomux_uart(); 354 if (CONFIG_IS_ENABLED(SATA)) 355 setup_sata(); 356 357 return 0; 358} 359 360#define PMIC_I2C_BUS 2 361 362int power_init_board(void) 363{ 364 struct udevice *dev; 365 int reg, ret; 366 367 ret = pmic_get("pfuze100@8", &dev); 368 if (ret < 0) { 369 debug("pmic_get() ret %d\n", ret); 370 return 0; 371 } 372 373 reg = pmic_reg_read(dev, PFUZE100_DEVICEID); 374 if (reg < 0) { 375 debug("pmic_reg_read() ret %d\n", reg); 376 return 0; 377 } 378 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 379 with_pmic = true; 380 381 /* Set VGEN2 to 1.5V and enable */ 382 reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL); 383 reg &= ~(LDO_VOL_MASK); 384 reg |= (LDOA_1_50V | (1 << (LDO_EN))); 385 pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg); 386 return 0; 387} 388 389/* 390 * Do not overwrite the console 391 * Use always serial for U-Boot console 392 */ 393int overwrite_console(void) 394{ 395 return 1; 396} 397 398#ifdef CONFIG_CMD_BMODE 399static const struct boot_mode board_boot_modes[] = { 400 /* 4 bit bus width */ 401 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 402 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 403 {NULL, 0}, 404}; 405#endif 406 407static bool is_revc1(void) 408{ 409 SETUP_IOMUX_PADS(rev_detection_pad); 410 gpio_request(REV_DETECTION, "REV_DETECT"); 411 gpio_direction_input(REV_DETECTION); 412 413 if (gpio_get_value(REV_DETECTION)) 414 return true; 415 else 416 return false; 417} 418 419static bool is_revd1(void) 420{ 421 if (with_pmic) 422 return true; 423 else 424 return false; 425} 426 427int board_late_init(void) 428{ 429#ifdef CONFIG_CMD_BMODE 430 add_board_boot_modes(board_boot_modes); 431#endif 432 433#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 434 if (is_mx6dqp()) 435 env_set("board_rev", "MX6QP"); 436 else if (is_mx6dq()) 437 env_set("board_rev", "MX6Q"); 438 else 439 env_set("board_rev", "MX6DL"); 440 441 if (is_revd1()) 442 env_set("board_name", "D1"); 443 else if (is_revc1()) 444 env_set("board_name", "C1"); 445 else 446 env_set("board_name", "B1"); 447#endif 448 setup_iomux_enet(); 449 450 if (is_revd1()) 451 puts("Board: Wandboard rev D1\n"); 452 else if (is_revc1()) 453 puts("Board: Wandboard rev C1\n"); 454 else 455 puts("Board: Wandboard rev B1\n"); 456 457 return 0; 458} 459 460int board_init(void) 461{ 462 /* address of boot parameters */ 463 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 464 465#if defined(CONFIG_VIDEO_IPUV3) 466 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info); 467 if (is_mx6dq() || is_mx6dqp()) { 468 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info); 469 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info); 470 } else { 471 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info); 472 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info); 473 } 474 475 setup_display(); 476#endif 477 478 return 0; 479} 480 481#ifdef CONFIG_SPL_LOAD_FIT 482int board_fit_config_name_match(const char *name) 483{ 484 if (is_mx6dq()) { 485 if (!strcmp(name, "imx6q-wandboard-revd1")) 486 return 0; 487 } else if (is_mx6dqp()) { 488 if (!strcmp(name, "imx6qp-wandboard-revd1")) 489 return 0; 490 } else if (is_mx6dl() || is_mx6solo()) { 491 if (!strcmp(name, "imx6dl-wandboard-revd1")) 492 return 0; 493 } 494 495 return -EINVAL; 496} 497#endif 498