1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 4 * Copyright (C) Jasbir Matharu 5 * Copyright (C) UDOO Team 6 * 7 * Author: Breno Lima <breno.lima@nxp.com> 8 * Author: Francesco Montefoschi <francesco.monte@gmail.com> 9 */ 10 11#include <init.h> 12#include <asm/arch/clock.h> 13#include <asm/arch/crm_regs.h> 14#include <asm/arch/imx-regs.h> 15#include <asm/arch/iomux.h> 16#include <asm/arch/mx6-pins.h> 17#include <asm/global_data.h> 18#include <asm/gpio.h> 19#include <asm/mach-imx/iomux-v3.h> 20#include <asm/sections.h> 21#include <dm.h> 22#include <env.h> 23#include <mmc.h> 24#include <fsl_esdhc_imx.h> 25#include <asm/arch/crm_regs.h> 26#include <asm/io.h> 27#include <asm/mach-imx/mxc_i2c.h> 28#include <asm/arch/sys_proto.h> 29#include <spl.h> 30#include <linux/delay.h> 31#include <linux/sizes.h> 32#include <common.h> 33#include <i2c.h> 34#include <power/pmic.h> 35#include <power/pfuze3000_pmic.h> 36#include <malloc.h> 37 38DECLARE_GLOBAL_DATA_PTR; 39 40enum { 41 UDOO_NEO_TYPE_BASIC, 42 UDOO_NEO_TYPE_BASIC_KS, 43 UDOO_NEO_TYPE_FULL, 44 UDOO_NEO_TYPE_EXTENDED, 45}; 46 47#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 48 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 49 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 50 51#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 52 PAD_CTL_SPEED_MED | \ 53 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 54 55#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ 56 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) 57 58#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 59 PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) 60 61#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ 62 PAD_CTL_DSE_40ohm) 63 64#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 65 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 66 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) 67#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \ 68 MUX_MODE_SION) 69 70#define OCRAM_START 0x8f8000 71 72int dram_init(void) 73{ 74 gd->ram_size = imx_ddr_size(); 75 return 0; 76} 77 78int power_init_board(void) 79{ 80 struct udevice *dev; 81 int ret, dev_id, rev_id; 82 83 ret = pmic_get("pfuze3000@8", &dev); 84 if (ret == -ENODEV) 85 return 0; 86 if (ret != 0) 87 return ret; 88 89 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); 90 rev_id = pmic_reg_read(dev, PFUZE3000_REVID); 91 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); 92 93 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); 94 95 return 0; 96} 97 98static iomux_v3_cfg_t const usdhc2_pads[] = { 99 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 /* CD pin */ 106 MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL), 107 /* Power */ 108 MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), 109}; 110 111static iomux_v3_cfg_t const phy_control_pads[] = { 112 /* 25MHz Ethernet PHY Clock */ 113 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | 114 MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 115}; 116 117static iomux_v3_cfg_t const wdog_b_pad = { 118 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), 119}; 120 121static iomux_v3_cfg_t const peri_3v3_pads[] = { 122 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), 123}; 124 125static int setup_fec(void) 126{ 127 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 128 int reg; 129 130 imx_iomux_v3_setup_multiple_pads(phy_control_pads, 131 ARRAY_SIZE(phy_control_pads)); 132 133 /* Reset PHY */ 134 gpio_request(IMX_GPIO_NR(2, 1), "enet_rst"); 135 gpio_direction_output(IMX_GPIO_NR(2, 1) , 0); 136 udelay(10000); 137 gpio_set_value(IMX_GPIO_NR(2, 1), 1); 138 udelay(100); 139 140 reg = readl(&anatop->pll_enet); 141 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; 142 writel(reg, &anatop->pll_enet); 143 144 return enable_fec_anatop_clock(0, ENET_25MHZ); 145} 146 147int board_init(void) 148{ 149 /* Address of boot parameters */ 150 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 151 152 /* 153 * Because kernel set WDOG_B mux before pad with the commone pinctrl 154 * framwork now and wdog reset will be triggered once set WDOG_B mux 155 * with default pad setting, we set pad setting here to workaround this. 156 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set 157 * as GPIO mux firstly here to workaround it. 158 */ 159 imx_iomux_v3_setup_pad(wdog_b_pad); 160 161 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ 162 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, 163 ARRAY_SIZE(peri_3v3_pads)); 164 165 /* Active high for ncp692 */ 166 gpio_request(IMX_GPIO_NR(4, 16), "ncp692"); 167 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); 168 169 setup_fec(); 170 171 return 0; 172} 173 174static struct fsl_esdhc_cfg usdhc_cfg[1] = { 175 {USDHC2_BASE_ADDR}, 176}; 177 178#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) 179#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2) 180 181int board_mmc_getcd(struct mmc *mmc) 182{ 183 return !gpio_get_value(USDHC2_CD_GPIO); 184} 185 186int board_mmc_init(struct bd_info *bis) 187{ 188 SETUP_IOMUX_PADS(usdhc2_pads); 189 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 190 usdhc_cfg[0].max_bus_width = 4; 191 gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr"); 192 gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd"); 193 gpio_direction_input(USDHC2_CD_GPIO); 194 gpio_direction_output(USDHC2_PWR_GPIO, 1); 195 196 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 197} 198 199static char *board_string(int type) 200{ 201 switch (type) { 202 case UDOO_NEO_TYPE_BASIC: 203 return "BASIC"; 204 case UDOO_NEO_TYPE_BASIC_KS: 205 return "BASICKS"; 206 case UDOO_NEO_TYPE_FULL: 207 return "FULL"; 208 case UDOO_NEO_TYPE_EXTENDED: 209 return "EXTENDED"; 210 } 211 return "UNDEFINED"; 212} 213 214/* Override the default implementation, DT model is not accurate */ 215int checkboard(void) 216{ 217 int *board_type = (int *)OCRAM_START; 218 219 printf("Board: UDOO Neo %s\n", board_string(*board_type)); 220 return 0; 221} 222 223int board_late_init(void) 224{ 225 int *board_type = (int *)OCRAM_START; 226 227#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 228 env_set("board_name", board_string(*board_type)); 229#endif 230 231 return 0; 232} 233 234#ifdef CONFIG_SPL_BUILD 235 236#include <linux/libfdt.h> 237#include <asm/arch/mx6-ddr.h> 238 239static const iomux_v3_cfg_t board_recognition_pads[] = { 240 /*Connected to R184*/ 241 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, 242 /*Connected to R185*/ 243 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, 244}; 245 246static int get_board_value(void) 247{ 248 int r184, r185; 249 250 imx_iomux_v3_setup_multiple_pads(board_recognition_pads, 251 ARRAY_SIZE(board_recognition_pads)); 252 253 gpio_request(IMX_GPIO_NR(4, 13), "r184"); 254 gpio_request(IMX_GPIO_NR(4, 0), "r185"); 255 gpio_direction_input(IMX_GPIO_NR(4, 13)); 256 gpio_direction_input(IMX_GPIO_NR(4, 0)); 257 258 r184 = gpio_get_value(IMX_GPIO_NR(4, 13)); 259 r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); 260 261 /* 262 * Machine selection - 263 * Machine r184, r185 264 * --------------------------------- 265 * Basic 0 0 266 * Basic Ks 0 1 267 * Full 1 0 268 * Extended 1 1 269 */ 270 271 return (r184 << 1) + r185; 272} 273 274static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { 275 .dram_dqm0 = 0x00000028, 276 .dram_dqm1 = 0x00000028, 277 .dram_dqm2 = 0x00000028, 278 .dram_dqm3 = 0x00000028, 279 .dram_ras = 0x00000020, 280 .dram_cas = 0x00000020, 281 .dram_odt0 = 0x00000020, 282 .dram_odt1 = 0x00000020, 283 .dram_sdba2 = 0x00000000, 284 .dram_sdcke0 = 0x00003000, 285 .dram_sdcke1 = 0x00003000, 286 .dram_sdclk_0 = 0x00000030, 287 .dram_sdqs0 = 0x00000028, 288 .dram_sdqs1 = 0x00000028, 289 .dram_sdqs2 = 0x00000028, 290 .dram_sdqs3 = 0x00000028, 291 .dram_reset = 0x00000020, 292}; 293 294static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { 295 .grp_addds = 0x00000020, 296 .grp_ddrmode_ctl = 0x00020000, 297 .grp_ddrpke = 0x00000000, 298 .grp_ddrmode = 0x00020000, 299 .grp_b0ds = 0x00000028, 300 .grp_b1ds = 0x00000028, 301 .grp_ctlds = 0x00000020, 302 .grp_ddr_type = 0x000c0000, 303 .grp_b2ds = 0x00000028, 304 .grp_b3ds = 0x00000028, 305}; 306 307static const struct mx6_mmdc_calibration neo_mmcd_calib = { 308 .p0_mpwldectrl0 = 0x000E000B, 309 .p0_mpwldectrl1 = 0x000E0010, 310 .p0_mpdgctrl0 = 0x41600158, 311 .p0_mpdgctrl1 = 0x01500140, 312 .p0_mprddlctl = 0x3A383E3E, 313 .p0_mpwrdlctl = 0x3A383C38, 314}; 315 316static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = { 317 .p0_mpwldectrl0 = 0x001E0022, 318 .p0_mpwldectrl1 = 0x001C0019, 319 .p0_mpdgctrl0 = 0x41540150, 320 .p0_mpdgctrl1 = 0x01440138, 321 .p0_mprddlctl = 0x403E4644, 322 .p0_mpwrdlctl = 0x3C3A4038, 323}; 324 325/* MT41K256M16 */ 326static struct mx6_ddr3_cfg neo_mem_ddr = { 327 .mem_speed = 1600, 328 .density = 4, 329 .width = 16, 330 .banks = 8, 331 .rowaddr = 15, 332 .coladdr = 10, 333 .pagesz = 2, 334 .trcd = 1375, 335 .trcmin = 4875, 336 .trasmin = 3500, 337}; 338 339/* MT41K128M16 */ 340static struct mx6_ddr3_cfg neo_basic_mem_ddr = { 341 .mem_speed = 1600, 342 .density = 2, 343 .width = 16, 344 .banks = 8, 345 .rowaddr = 14, 346 .coladdr = 10, 347 .pagesz = 2, 348 .trcd = 1375, 349 .trcmin = 4875, 350 .trasmin = 3500, 351}; 352 353static void ccgr_init(void) 354{ 355 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 356 357 writel(0xFFFFFFFF, &ccm->CCGR0); 358 writel(0xFFFFFFFF, &ccm->CCGR1); 359 writel(0xFFFFFFFF, &ccm->CCGR2); 360 writel(0xFFFFFFFF, &ccm->CCGR3); 361 writel(0xFFFFFFFF, &ccm->CCGR4); 362 writel(0xFFFFFFFF, &ccm->CCGR5); 363 writel(0xFFFFFFFF, &ccm->CCGR6); 364 writel(0xFFFFFFFF, &ccm->CCGR7); 365} 366 367static void spl_dram_init(void) 368{ 369 int *board_type = (int *)OCRAM_START; 370 371 struct mx6_ddr_sysinfo sysinfo = { 372 .dsize = 1, /* width of data bus: 1 = 32 bits */ 373 .cs_density = 24, 374 .ncs = 1, 375 .cs1_mirror = 0, 376 .rtt_wr = 2, 377 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ 378 .walat = 1, /* Write additional latency */ 379 .ralat = 5, /* Read additional latency */ 380 .mif3_mode = 3, /* Command prediction working mode */ 381 .bi_on = 1, /* Bank interleaving enabled */ 382 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 383 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 384 }; 385 386 *board_type = get_board_value(); 387 388 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); 389 if (*board_type == UDOO_NEO_TYPE_BASIC || 390 *board_type == UDOO_NEO_TYPE_BASIC_KS) 391 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib, 392 &neo_basic_mem_ddr); 393 else 394 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr); 395} 396 397void board_init_f(ulong dummy) 398{ 399 ccgr_init(); 400 401 /* setup AIPS and disable watchdog */ 402 arch_cpu_init(); 403 404 /* setup GP timer */ 405 timer_init(); 406 407 /* Enable device tree and early DM support*/ 408 spl_early_init(); 409 410 /* UART clocks enabled and gd valid - init serial console */ 411 preloader_console_init(); 412 413 /* DDR initialization */ 414 spl_dram_init(); 415 416 /* Clear the BSS. */ 417 memset(__bss_start, 0, __bss_end - __bss_start); 418 419 /* load/boot image from boot device */ 420 board_init_r(NULL, 0); 421} 422 423#endif 424