1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com> 4 * 5 */ 6 7#include <i2c.h> 8#include <miiphy.h> 9#include <netdev.h> 10#include <asm/io.h> 11#include <asm/arch/cpu.h> 12#include <asm/arch/soc.h> 13#include <linux/bitops.h> 14 15#include "../drivers/ddr/marvell/a38x/ddr3_init.h" 16#include <../serdes/a38x/high_speed_env_spec.h> 17 18DECLARE_GLOBAL_DATA_PTR; 19 20/* 21 * Those N2350_GPP_xx values and defines in board_serdes_map, and board_topology_map 22 * are taken from the Marvell U-Boot version "u-boot-a38x-2015T1_p18_Thecus" 23 */ 24 25#define N2350_GPP_OUT_ENA_LOW (~(BIT(20) | BIT(21) | BIT(24))) 26#define N2350_GPP_OUT_ENA_MID (~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22))) 27#define N2350_GPP_OUT_VAL_LOW (BIT(21) | BIT(24)) 28#define N2350_GPP_OUT_VAL_MID (BIT(0) | BIT(12) | BIT(13) | BIT(16)) 29#define N2350_GPP_POL_LOW 0x0 30#define N2350_GPP_POL_MID 0x0 31 32static struct serdes_map board_serdes_map[] = { 33 { SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 34 { SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 35 { SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 36 { DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 37 { USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 38 { USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 39}; 40 41int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) 42{ 43 *serdes_map_array = board_serdes_map; 44 *count = ARRAY_SIZE(board_serdes_map); 45 return 0; 46} 47 48/* 49 * Define the DDR layout / topology here in the board file. This will 50 * be used by the DDR4 init code in the SPL U-Boot version to configure 51 * the DDR4 controller. 52 */ 53 54static struct mv_ddr_topology_map board_topology_map = { 55 DEBUG_LEVEL_ERROR, 56 0x1, /* active interfaces */ 57 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 58 { { { {0x1, 0, 0, 0}, 59 {0x1, 0, 0, 0}, 60 {0x1, 0, 0, 0}, 61 {0x1, 0, 0, 0}, 62 {0x1, 0, 0, 0} }, 63 SPEED_BIN_DDR_1866L, /* speed_bin */ 64 MV_DDR_DEV_WIDTH_16BIT, /* memory_width - 16 bits */ 65 MV_DDR_DIE_CAP_4GBIT, /* mem_size - N2350 board has 2x512MB DRAM banks */ 66 MV_DDR_FREQ_800, /* frequency */ 67 0, 0, /* cas_wl cas_l */ 68 MV_DDR_TEMP_LOW, /* temperature */ 69 MV_DDR_TIM_DEFAULT} }, /* timing */ 70 BUS_MASK_32BIT, /* Busses mask */ 71 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 72 NOT_COMBINED, /* ddr twin-die combined */ 73 { {0} }, /* raw spd data */ 74 {0} /* timing parameters */ 75}; 76 77struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) 78{ 79 /* Return the board topology as defined in the board code */ 80 return &board_topology_map; 81} 82 83int board_early_init_f(void) 84{ 85 /* Those MPP values are taken from the Marvell U-Boot version 86 * "u-boot-a38x-2015T1_p18_Thecus" 87 */ 88 89 /* Configure MPP */ 90 writel(0x50111111, MVEBU_MPP_BASE + 0x00); /* MPP0_7 */ 91 writel(0x00555555, MVEBU_MPP_BASE + 0x04); /* MPP8_15 */ 92 writel(0x55000000, MVEBU_MPP_BASE + 0x08); /* MPP16_23 */ 93 writel(0x05050050, MVEBU_MPP_BASE + 0x0c); /* MPP24_31 */ 94 writel(0x05555555, MVEBU_MPP_BASE + 0x10); /* MPP32_39 */ 95 writel(0x00000565, MVEBU_MPP_BASE + 0x14); /* MPP40_47 */ 96 writel(0x00000000, MVEBU_MPP_BASE + 0x18); /* MPP48_55 */ 97 writel(0x00004444, MVEBU_MPP_BASE + 0x1c); /* MPP56_63 */ 98 99 /* Set GPP Out value */ 100 writel(N2350_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 101 writel(N2350_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 102 103 /* Set GPP Polarity */ 104 writel(N2350_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); 105 writel(N2350_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); 106 107 /* Set GPP Out Enable */ 108 writel(N2350_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 109 writel(N2350_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 110 111 return 0; 112} 113 114int board_init(void) 115{ 116 /* Address of boot parameters */ 117 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 118 119 return 0; 120} 121 122int board_eth_init(struct bd_info *bis) 123{ 124 cpu_eth_init(bis); /* Built in controller(s) come first */ 125 return pci_eth_init(bis); 126} 127