1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Board functions for Sysam AMCORE (MCF5307 based) board
4 *
5 * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
6 *
7 * This file copies memory testdram() from sandburst/common/sb_common.c
8 */
9
10#include <common.h>
11#include <init.h>
12#include <asm/global_data.h>
13#include <asm/immap.h>
14#include <asm/io.h>
15#include <dm.h>
16#include <dm/platform_data/serial_coldfire.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20void init_lcd(void)
21{
22	/* setup for possible K0108 lcd connected on the parallel port */
23	sim_t *sim = (sim_t *)(MMAP_SIM);
24
25	out_be16(&sim->par, 0x300);
26
27	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
28
29	out_be16(&gpio->paddr, 0xfcff);
30	out_be16(&gpio->padat, 0x0c00);
31}
32
33int checkboard(void)
34{
35	puts("Board: ");
36	puts("AMCORE v.001(alpha)\n");
37
38	init_lcd();
39
40	return 0;
41}
42
43/*
44 * in dram_init we are here executing from flash
45 * case 1:
46 * is with no ACR/flash cache enabled
47 * nop = 40ns (scope measured)
48 */
49void fudelay(int usec)
50{
51	while (usec--)
52		asm volatile ("nop");
53}
54
55int dram_init(void)
56{
57	u32 dramsize, RC;
58
59	sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
60
61	/*
62	 * SDRAM  MT48LC4M32B2 details
63	 * Memory block 0: 16 MB of SDRAM at address $00000000
64	 * Port size: 32-bit port
65	 *
66	 * Memory block 0 wired as follows:
67	 * CPU   : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
68	 * SDRAM :  A0  A1  A2  A3  A4  A5  A6 A7  A8  A9 A10 A11 BA0 BA1
69	 *
70	 * Ensure that there is a delay of at least 100 microseconds from
71	 * processor reset to the following code so that the SDRAM is ready
72	 * for commands.
73	 */
74	fudelay(100);
75
76	/*
77	 * DCR
78	 * set proper  RC as per specification
79	 */
80	RC = (CFG_SYS_CPU_CLK / 1000000) >> 1;
81	RC = (RC * 15) >> 4;
82
83	/* 0x8000 is the faster option */
84	out_be16(&dc->dcr, 0x8200 | RC);
85
86	/*
87	 * DACR0, page mode continuous, CMD on A20 0x0300
88	 */
89	out_be32(&dc->dacr0, 0x00003304);
90
91	dramsize = ((CFG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
92	out_be32(&dc->dmr0,  dramsize|1);
93
94	/* issue a PRECHARGE ALL */
95	out_be32(&dc->dacr0, 0x0000330c);
96	out_be32((u32 *)0x00000004, 0xbeaddeed);
97	/* issue AUTOREFRESH */
98	out_be32(&dc->dacr0, 0x0000b304);
99	/* let refresh occur */
100	fudelay(1);
101
102	out_be32(&dc->dacr0, 0x0000b344);
103	out_be32((u32 *)0x00000c00, 0xbeaddeed);
104
105	gd->ram_size = get_ram_size(CFG_SYS_SDRAM_BASE,
106				    CFG_SYS_SDRAM_SIZE);
107
108	return 0;
109}
110
111static struct coldfire_serial_plat mcf5307_serial_plat = {
112	.base = CFG_SYS_UART_BASE,
113	.port = 0,
114	.baudrate = CONFIG_BAUDRATE,
115};
116
117U_BOOT_DRVINFO(coldfire_serial) = {
118	.name = "serial_coldfire",
119	.plat = &mcf5307_serial_plat,
120};
121