1/*
2 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include <config.h>
8#include <system-constants.h>
9
10MEMORY {
11	ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
12	RAM : ORIGIN = RAM_DATA_BASE, LENGTH = RAM_DATA_SIZE
13}
14
15OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
16OUTPUT_ARCH(arc)
17ENTRY(_start)
18SECTIONS
19{
20	. = CONFIG_SYS_MONITOR_BASE;
21	__image_copy_start = .;
22	.ivt :
23	{
24		__ivt_start = .;
25		KEEP(*(.ivt));
26		__ivt_end = .;
27	} > ROM
28
29	. = ALIGN(1024);
30	.text :	{
31		__text_start = .;
32		arch/arc/lib/start.o (.text*)
33		*(.text*)
34		__text_end = .;
35	} > ROM
36
37	. = ALIGN(4);
38	.rodata : {
39		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
40	} > ROM
41
42	. = ALIGN(4);
43	__u_boot_list : {
44		KEEP(*(SORT(__u_boot_list*)));
45
46		/* Mark RAM's LMA */
47		. = ALIGN(4);
48		__rom_end = .;
49	} > ROM
50
51	.data : {
52		/* Mark RAM's VMA */
53		. = ALIGN(4);
54
55		/*
56		 * Everything between __ram_start and __ram_start will be
57		 * copied from ROM to RAM in board_early_init_f().
58		 */
59		__ram_start = .;
60
61		*(.data*)
62
63		__ram_end = .;
64	} > RAM AT > ROM
65
66	.bss : {
67		. = ALIGN(1024);
68		__bss_start = .;
69		*(.bss*)
70		__bss_end = .;
71	} > RAM
72
73	/* Keep relocation-related symbols to make linker happy */
74	__rel_dyn_start = .;
75	__rel_dyn_end = .;
76	__image_copy_end = .;
77	__init_end = .;
78}
79