1// SPDX-License-Identifier: GPL-2.0 2/* 3 * board/renesas/silk/silk.c 4 * 5 * Copyright (C) 2015 Renesas Electronics Corporation 6 * Copyright (C) 2015 Cogent Embedded, Inc. 7 */ 8 9#include <cpu_func.h> 10#include <env.h> 11#include <hang.h> 12#include <init.h> 13#include <malloc.h> 14#include <dm.h> 15#include <asm/global_data.h> 16#include <dm/platform_data/serial_sh.h> 17#include <env_internal.h> 18#include <asm/processor.h> 19#include <asm/mach-types.h> 20#include <asm/io.h> 21#include <linux/bitops.h> 22#include <linux/delay.h> 23#include <linux/errno.h> 24#include <asm/arch/sys_proto.h> 25#include <asm/gpio.h> 26#include <asm/arch/renesas.h> 27#include <asm/arch/rcar-mstp.h> 28#include <netdev.h> 29#include <miiphy.h> 30#include <i2c.h> 31#include <div64.h> 32#include "qos.h" 33 34DECLARE_GLOBAL_DATA_PTR; 35 36void s_init(void) 37{ 38 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 39 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 40 41 /* Watchdog init */ 42 writel(0xA5A5A500, &rwdt->rwtcsra); 43 writel(0xA5A5A500, &swdt->swtcsra); 44 45 /* QoS */ 46 qos_init(); 47} 48 49#define TMU0_MSTP125 BIT(25) 50#define MMC0_MSTP315 BIT(15) 51 52#define SD1CKCR 0xE6150078 53#define SD_97500KHZ 0x7 54 55int board_early_init_f(void) 56{ 57 /* TMU */ 58 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 59 60 /* Set SD1 to the 97.5MHz */ 61 writel(SD_97500KHZ, SD1CKCR); 62 63 return 0; 64} 65 66#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */ 67 68int board_init(void) 69{ 70 /* adress of boot parameters */ 71 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; 72 73 /* Force ethernet PHY out of reset */ 74 gpio_request(ETHERNET_PHY_RESET, "phy_reset"); 75 gpio_direction_output(ETHERNET_PHY_RESET, 0); 76 mdelay(20); 77 gpio_direction_output(ETHERNET_PHY_RESET, 1); 78 udelay(1); 79 80 return 0; 81} 82 83int dram_init(void) 84{ 85 if (fdtdec_setup_mem_size_base() != 0) 86 return -EINVAL; 87 88 return 0; 89} 90 91int dram_init_banksize(void) 92{ 93 fdtdec_setup_memory_banksize(); 94 95 return 0; 96} 97 98/* porter has KSZ8041RNLI */ 99#define PHY_CONTROL1 0x1E 100#define PHY_LED_MODE 0xC000 101#define PHY_LED_MODE_ACK 0x4000 102int board_phy_config(struct phy_device *phydev) 103{ 104 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 105 ret &= ~PHY_LED_MODE; 106 ret |= PHY_LED_MODE_ACK; 107 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 108 109 return 0; 110} 111 112void reset_cpu(void) 113{ 114 struct udevice *dev; 115 const u8 pmic_bus = 1; 116 const u8 pmic_addr = 0x5a; 117 u8 data; 118 int ret; 119 120 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); 121 if (ret) 122 hang(); 123 124 ret = dm_i2c_read(dev, 0x13, &data, 1); 125 if (ret) 126 hang(); 127 128 data |= BIT(1); 129 130 ret = dm_i2c_write(dev, 0x13, &data, 1); 131 if (ret) 132 hang(); 133} 134 135enum env_location env_get_location(enum env_operation op, int prio) 136{ 137 const u32 load_magic = 0xb33fc0de; 138 139 /* Block environment access if loaded using JTAG */ 140 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && 141 (op != ENVOP_INIT)) 142 return ENVL_UNKNOWN; 143 144 if (prio) 145 return ENVL_UNKNOWN; 146 147 return ENVL_SPI_FLASH; 148} 149