1// SPDX-License-Identifier: GPL-2.0
2/*
3 * board/renesas/porter/porter_spl.c
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8#include <cpu_func.h>
9#include <init.h>
10#include <malloc.h>
11#include <dm/platform_data/serial_sh.h>
12#include <asm/processor.h>
13#include <asm/mach-types.h>
14#include <asm/io.h>
15#include <linux/bitops.h>
16#include <linux/errno.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/gpio.h>
19#include <asm/arch/renesas.h>
20#include <asm/arch/rcar-mstp.h>
21
22#include <spl.h>
23
24#define TMU0_MSTP125	BIT(25)
25#define SCIF0_MSTP721	BIT(21)
26#define QSPI_MSTP917	BIT(17)
27
28#define SD2CKCR		0xE615026C
29#define SD_97500KHZ	0x7
30
31struct reg_config {
32	u16	off;
33	u32	val;
34};
35
36static void dbsc_wait(u16 reg)
37{
38	static const u32 dbsc3_0_base = DBSC3_0_BASE;
39	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
40
41	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
42		;
43
44	while (!(readl(dbsc3_1_base + reg) & BIT(0)))
45		;
46}
47
48static void spl_init_sys(void)
49{
50	u32 r0 = 0;
51
52	writel(0xa5a5a500, 0xe6020004);
53	writel(0xa5a5a500, 0xe6030004);
54
55	asm volatile(
56		/* ICIALLU - Invalidate I$ to PoU */
57		"mcr	15, 0, %0, cr7, cr5, 0	\n"
58		/* BPIALL - Invalidate branch predictors */
59		"mcr	15, 0, %0, cr7, cr5, 6	\n"
60		/* Set SCTLR[IZ] */
61		"mrc	15, 0, %0, cr1, cr0, 0	\n"
62		"orr	%0, #0x1800		\n"
63		"mcr	15, 0, %0, cr1, cr0, 0	\n"
64		"isb	sy			\n"
65		:"=r"(r0));
66}
67
68static void spl_init_pfc(void)
69{
70	static const struct reg_config pfc_with_unlock[] = {
71		{ 0x0090, 0x60000000 },
72		{ 0x0094, 0x60000000 },
73		{ 0x0098, 0x00800200 },
74		{ 0x009c, 0x00000000 },
75		{ 0x0020, 0x00000000 },
76		{ 0x0024, 0x00000000 },
77		{ 0x0028, 0x000244c8 },
78		{ 0x002c, 0x00000000 },
79		{ 0x0030, 0x00002400 },
80		{ 0x0034, 0x01520000 },
81		{ 0x0038, 0x00724003 },
82		{ 0x003c, 0x00000000 },
83		{ 0x0040, 0x00000000 },
84		{ 0x0044, 0x00000000 },
85		{ 0x0048, 0x00000000 },
86		{ 0x004c, 0x00000000 },
87		{ 0x0050, 0x00000000 },
88		{ 0x0054, 0x00000000 },
89		{ 0x0058, 0x00000000 },
90		{ 0x005c, 0x00000000 },
91		{ 0x0160, 0x00000000 },
92		{ 0x0004, 0xffffffff },
93		{ 0x0008, 0x00ec3fff },
94		{ 0x000c, 0x3bc001e7 },
95		{ 0x0010, 0x5bffffff },
96		{ 0x0014, 0x1ffffffb },
97		{ 0x0018, 0x01bffff0 },
98		{ 0x001c, 0xcf7fffff },
99		{ 0x0074, 0x0381fc00 },
100	};
101
102	static const struct reg_config pfc_without_unlock[] = {
103		{ 0x0100, 0xffffffdf },
104		{ 0x0104, 0xc883c3ff },
105		{ 0x0108, 0x1201f3c9 },
106		{ 0x010c, 0x00000000 },
107		{ 0x0110, 0xffffeb04 },
108		{ 0x0114, 0xc003ffff },
109		{ 0x0118, 0x0800000f },
110		{ 0x011c, 0x00187ff0 },
111	};
112
113	static const u32 pfc_base = 0xe6060000;
114
115	unsigned int i;
116
117	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
118		writel(~pfc_with_unlock[i].val, pfc_base);
119		writel(pfc_with_unlock[i].val,
120		       pfc_base | pfc_with_unlock[i].off);
121	}
122
123	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
124		writel(pfc_without_unlock[i].val,
125		       pfc_base | pfc_without_unlock[i].off);
126}
127
128static void spl_init_gpio(void)
129{
130	static const u16 gpio_offs[] = {
131		0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
132	};
133
134	static const struct reg_config gpio_set[] = {
135		{ 0x2000, 0x04381000 },
136		{ 0x5000, 0x00000000 },
137		{ 0x5800, 0x000e0000 },
138	};
139
140	static const struct reg_config gpio_clr[] = {
141		{ 0x1000, 0x00000000 },
142		{ 0x2000, 0x04381010 },
143		{ 0x3000, 0x00000000 },
144		{ 0x4000, 0x00000000 },
145		{ 0x5000, 0x00400000 },
146		{ 0x5400, 0x00000000 },
147		{ 0x5800, 0x000e0380 },
148	};
149
150	static const u32 gpio_base = 0xe6050000;
151
152	unsigned int i;
153
154	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
155		writel(0, gpio_base | 0x20 | gpio_offs[i]);
156
157	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
158		writel(0, gpio_base | 0x00 | gpio_offs[i]);
159
160	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
161		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
162
163	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
164		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
165}
166
167static void spl_init_lbsc(void)
168{
169	static const struct reg_config lbsc_config[] = {
170		{ 0x00, 0x00000020 },
171		{ 0x08, 0x00002020 },
172		{ 0x30, 0x2a103320 },
173		{ 0x38, 0xff70ff70 },
174	};
175
176	static const u16 lbsc_offs[] = {
177		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
178	};
179
180	static const u32 lbsc_base = 0xfec00200;
181
182	unsigned int i;
183
184	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
185		writel(lbsc_config[i].val,
186		       lbsc_base | lbsc_config[i].off);
187		writel(lbsc_config[i].val,
188		       lbsc_base | (lbsc_config[i].off + 4));
189	}
190
191	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
192		writel(0, lbsc_base | lbsc_offs[i]);
193}
194
195static void spl_init_dbsc(void)
196{
197	static const struct reg_config dbsc_config1[] = {
198		{ 0x0280, 0x0000a55a },
199		{ 0x4000, 0x0000a55a },
200		{ 0x4008, 0x00000001 },
201		{ 0x0018, 0x21000000 },
202		{ 0x0018, 0x11000000 },
203		{ 0x0018, 0x10000000 },
204		{ 0x0290, 0x00000001 },
205		{ 0x02a0, 0x80000000 },
206		{ 0x0290, 0x00000004 },
207	};
208
209	static const struct reg_config dbsc_config2[] = {
210		{ 0x0290, 0x00000006 },
211		{ 0x02a0, 0x0001c000 },
212	};
213
214	static const struct reg_config dbsc_config3r0d0[] = {
215		{ 0x0290, 0x0000000f },
216		{ 0x02a0, 0x00181885 },
217		{ 0x0290, 0x00000070 },
218		{ 0x02a0, 0x7c000887 },
219		{ 0x0290, 0x00000080 },
220		{ 0x02a0, 0x7c000887 },
221		{ 0x0290, 0x00000090 },
222		{ 0x02a0, 0x7c000887 },
223		{ 0x0290, 0x000000a0 },
224		{ 0x02a0, 0x7c000887 },
225		{ 0x0290, 0x000000b0 },
226		{ 0x02a0, 0x7c000880 },
227		{ 0x0290, 0x000000c0 },
228		{ 0x02a0, 0x7c000880 },
229		{ 0x0290, 0x000000d0 },
230		{ 0x02a0, 0x7c000880 },
231		{ 0x0290, 0x000000e0 },
232		{ 0x02a0, 0x7c000880 },
233	};
234	static const struct reg_config dbsc_config3r0d1[] = {
235		{ 0x0290, 0x0000000f },
236		{ 0x02a0, 0x00181885 },
237		{ 0x0290, 0x00000070 },
238		{ 0x02a0, 0x7c000887 },
239		{ 0x0290, 0x00000080 },
240		{ 0x02a0, 0x7c000887 },
241		{ 0x0290, 0x00000090 },
242		{ 0x02a0, 0x7c000887 },
243		{ 0x0290, 0x000000a0 },
244		{ 0x02a0, 0x7c000887 },
245	};
246
247	static const struct reg_config dbsc_config3r2[] = {
248		{ 0x0290, 0x0000000f },
249		{ 0x02a0, 0x00181224 },
250	};
251
252	static const struct reg_config dbsc_config4[] = {
253		{ 0x0290, 0x00000010 },
254		{ 0x02a0, 0xf004649b },
255		{ 0x0290, 0x00000061 },
256		{ 0x02a0, 0x0000006d },
257		{ 0x0290, 0x00000001 },
258		{ 0x02a0, 0x00000073 },
259		{ 0x0020, 0x00000007 },
260		{ 0x0024, 0x0f030a02 },
261		{ 0x0030, 0x00000001 },
262		{ 0x00b0, 0x00000000 },
263		{ 0x0040, 0x0000000b },
264		{ 0x0044, 0x00000008 },
265		{ 0x0048, 0x00000000 },
266		{ 0x0050, 0x0000000b },
267		{ 0x0054, 0x000c000b },
268		{ 0x0058, 0x00000027 },
269		{ 0x005c, 0x0000001c },
270		{ 0x0060, 0x00000006 },
271		{ 0x0064, 0x00000020 },
272		{ 0x0068, 0x00000008 },
273		{ 0x006c, 0x0000000c },
274		{ 0x0070, 0x00000009 },
275		{ 0x0074, 0x00000012 },
276		{ 0x0078, 0x000000d0 },
277		{ 0x007c, 0x00140005 },
278		{ 0x0080, 0x00050004 },
279		{ 0x0084, 0x70233005 },
280		{ 0x0088, 0x000c0000 },
281		{ 0x008c, 0x00000200 },
282		{ 0x0090, 0x00000040 },
283		{ 0x0100, 0x00000001 },
284		{ 0x00c0, 0x00020001 },
285		{ 0x00c8, 0x20042004 },
286		{ 0x0380, 0x00020002 },
287		{ 0x0390, 0x0000001f },
288	};
289
290	static const struct reg_config dbsc_config5[] = {
291		{ 0x0244, 0x00000011 },
292		{ 0x0290, 0x00000003 },
293		{ 0x02a0, 0x0300c561 },
294		{ 0x0290, 0x00000023 },
295		{ 0x02a0, 0x00fcdb60 },
296		{ 0x0290, 0x00000011 },
297		{ 0x02a0, 0x1000040b },
298		{ 0x0290, 0x00000012 },
299		{ 0x02a0, 0x9d9cbb66 },
300		{ 0x0290, 0x00000013 },
301		{ 0x02a0, 0x1a868400 },
302		{ 0x0290, 0x00000014 },
303		{ 0x02a0, 0x300214d8 },
304		{ 0x0290, 0x00000015 },
305		{ 0x02a0, 0x00000d70 },
306		{ 0x0290, 0x00000016 },
307		{ 0x02a0, 0x00000006 },
308		{ 0x0290, 0x00000017 },
309		{ 0x02a0, 0x00000018 },
310		{ 0x0290, 0x0000001a },
311		{ 0x02a0, 0x910035c7 },
312		{ 0x0290, 0x00000004 },
313	};
314
315	static const struct reg_config dbsc_config6[] = {
316		{ 0x0290, 0x00000001 },
317		{ 0x02a0, 0x00000181 },
318		{ 0x0018, 0x11000000 },
319		{ 0x0290, 0x00000004 },
320	};
321
322	static const struct reg_config dbsc_config7[] = {
323		{ 0x0290, 0x00000001 },
324		{ 0x02a0, 0x0000fe01 },
325		{ 0x0304, 0x00000000 },
326		{ 0x00f4, 0x01004c20 },
327		{ 0x00f8, 0x014a00b9 },
328		{ 0x00e0, 0x00000140 },
329		{ 0x00e4, 0x00081860 },
330		{ 0x00e8, 0x00010000 },
331		{ 0x0290, 0x00000004 },
332	};
333
334	static const struct reg_config dbsc_config8[] = {
335		{ 0x0014, 0x00000001 },
336		{ 0x0290, 0x00000010 },
337		{ 0x02a0, 0xf00464db },
338		{ 0x4008, 0x00000000 },
339		{ 0x4000, 0x00000000 },
340		{ 0x0010, 0x00000001 },
341		{ 0x0280, 0x00000000 },
342	};
343
344	static const u32 dbsc3_0_base = DBSC3_0_BASE;
345	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
346	static const u32 prr_base = 0xff000044;
347	const u16 prr_rev = readl(prr_base) & 0x7fff;
348	unsigned int i;
349
350	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
351		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
352		writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
353	}
354
355	dbsc_wait(0x2a0);
356
357	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
358		writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
359		writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
360	}
361
362	if (prr_rev == 0x4700) {
363		for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
364			writel(dbsc_config3r0d0[i].val,
365				dbsc3_0_base | dbsc_config3r0d0[i].off);
366		}
367		for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
368			writel(dbsc_config3r0d1[i].val,
369				dbsc3_1_base | dbsc_config3r0d1[i].off);
370		}
371	} else if (prr_rev != 0x4710) {
372		for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
373			writel(dbsc_config3r2[i].val,
374				dbsc3_0_base | dbsc_config3r2[i].off);
375			writel(dbsc_config3r2[i].val,
376				dbsc3_1_base | dbsc_config3r2[i].off);
377		}
378	}
379
380	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
381		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
382		writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
383	}
384
385	dbsc_wait(0x240);
386
387	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
388		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
389		writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
390	}
391
392	dbsc_wait(0x2a0);
393
394	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
395		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
396		writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
397	}
398
399	dbsc_wait(0x2a0);
400
401	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
402		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
403		writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
404	}
405
406	dbsc_wait(0x2a0);
407
408	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
409		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
410		writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
411	}
412
413}
414
415static void spl_init_qspi(void)
416{
417	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
418
419	static const u32 qspi_base = 0xe6b10000;
420
421	writeb(0x08, qspi_base + 0x00);
422	writeb(0x00, qspi_base + 0x01);
423	writeb(0x06, qspi_base + 0x02);
424	writeb(0x01, qspi_base + 0x0a);
425	writeb(0x00, qspi_base + 0x0b);
426	writeb(0x00, qspi_base + 0x0c);
427	writeb(0x00, qspi_base + 0x0d);
428	writeb(0x00, qspi_base + 0x0e);
429
430	writew(0xe080, qspi_base + 0x10);
431
432	writeb(0xc0, qspi_base + 0x18);
433	writeb(0x00, qspi_base + 0x18);
434	writeb(0x00, qspi_base + 0x08);
435	writeb(0x48, qspi_base + 0x00);
436}
437
438void board_init_f(ulong dummy)
439{
440	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
441	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
442
443	/*
444	 * SD0 clock is set to 97.5MHz by default.
445	 * Set SD2 to the 97.5MHz as well.
446	 */
447	writel(SD_97500KHZ, SD2CKCR);
448
449	spl_init_sys();
450	spl_init_pfc();
451	spl_init_gpio();
452	spl_init_lbsc();
453	spl_init_dbsc();
454	spl_init_qspi();
455}
456
457void spl_board_init(void)
458{
459	/* UART clocks enabled and gd valid - init serial console */
460	preloader_console_init();
461}
462
463void board_boot_order(u32 *spl_boot_list)
464{
465	const u32 jtag_magic = 0x1337c0de;
466	const u32 load_magic = 0xb33fc0de;
467
468	/*
469	 * If JTAG probe sets special word at 0xe6300020, then it must
470	 * put U-Boot into RAM and SPL will start it from RAM.
471	 */
472	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
473		printf("JTAG boot detected!\n");
474
475		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
476			;
477
478		spl_boot_list[0] = BOOT_DEVICE_RAM;
479		spl_boot_list[1] = BOOT_DEVICE_NONE;
480
481		return;
482	}
483
484	/* Boot from SPI NOR with YMODEM UART fallback. */
485	spl_boot_list[0] = BOOT_DEVICE_SPI;
486	spl_boot_list[1] = BOOT_DEVICE_UART;
487	spl_boot_list[2] = BOOT_DEVICE_NONE;
488}
489
490void reset_cpu(void)
491{
492}
493