1// SPDX-License-Identifier: GPL-2.0 2/* 3 * board/renesas/koelsch/koelsch_spl.c 4 * 5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 6 */ 7 8#include <cpu_func.h> 9#include <init.h> 10#include <malloc.h> 11#include <dm/platform_data/serial_sh.h> 12#include <asm/processor.h> 13#include <asm/mach-types.h> 14#include <asm/io.h> 15#include <linux/bitops.h> 16#include <linux/errno.h> 17#include <asm/arch/sys_proto.h> 18#include <asm/gpio.h> 19#include <asm/arch/renesas.h> 20#include <asm/arch/rcar-mstp.h> 21 22#include <spl.h> 23 24#define TMU0_MSTP125 BIT(25) 25#define SCIF0_MSTP721 BIT(21) 26#define QSPI_MSTP917 BIT(17) 27 28#define SD2CKCR 0xE615026C 29#define SD_97500KHZ 0x7 30 31struct reg_config { 32 u16 off; 33 u32 val; 34}; 35 36static void dbsc_wait(u16 reg) 37{ 38 static const u32 dbsc3_0_base = DBSC3_0_BASE; 39 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; 40 41 while (!(readl(dbsc3_0_base + reg) & BIT(0))) 42 ; 43 44 while (!(readl(dbsc3_1_base + reg) & BIT(0))) 45 ; 46} 47 48static void spl_init_sys(void) 49{ 50 u32 r0 = 0; 51 52 writel(0xa5a5a500, 0xe6020004); 53 writel(0xa5a5a500, 0xe6030004); 54 55 asm volatile( 56 /* ICIALLU - Invalidate I$ to PoU */ 57 "mcr 15, 0, %0, cr7, cr5, 0 \n" 58 /* BPIALL - Invalidate branch predictors */ 59 "mcr 15, 0, %0, cr7, cr5, 6 \n" 60 /* Set SCTLR[IZ] */ 61 "mrc 15, 0, %0, cr1, cr0, 0 \n" 62 "orr %0, #0x1800 \n" 63 "mcr 15, 0, %0, cr1, cr0, 0 \n" 64 "isb sy \n" 65 :"=r"(r0)); 66} 67 68static void spl_init_pfc(void) 69{ 70 static const struct reg_config pfc_with_unlock[] = { 71 { 0x0090, 0x60000000 }, 72 { 0x0094, 0x60000000 }, 73 { 0x0098, 0x00800200 }, 74 { 0x009c, 0x00000000 }, 75 { 0x0020, 0x00000000 }, 76 { 0x0024, 0x00000000 }, 77 { 0x0028, 0x000244c8 }, 78 { 0x002c, 0x00000000 }, 79 { 0x0030, 0x00002400 }, 80 { 0x0034, 0x01520000 }, 81 { 0x0038, 0x00724003 }, 82 { 0x003c, 0x00000000 }, 83 { 0x0040, 0x00000000 }, 84 { 0x0044, 0x00000000 }, 85 { 0x0048, 0x00000000 }, 86 { 0x004c, 0x00000000 }, 87 { 0x0050, 0x00000000 }, 88 { 0x0054, 0x00000000 }, 89 { 0x0058, 0x00000000 }, 90 { 0x005c, 0x00000000 }, 91 { 0x0160, 0x00000000 }, 92 { 0x0004, 0xffffffff }, 93 { 0x0008, 0x00ec3fff }, 94 { 0x000c, 0x3bc001e7 }, 95 { 0x0010, 0x5bffffff }, 96 { 0x0014, 0x1ffffffb }, 97 { 0x0018, 0x01bffff0 }, 98 { 0x001c, 0xcf7fffff }, 99 { 0x0074, 0x0381fc00 }, 100 }; 101 102 static const struct reg_config pfc_without_unlock[] = { 103 { 0x0100, 0xffffffdf }, 104 { 0x0104, 0xc883c3ff }, 105 { 0x0108, 0x1201f3c9 }, 106 { 0x010c, 0x00000000 }, 107 { 0x0110, 0xffffeb04 }, 108 { 0x0114, 0xc003ffff }, 109 { 0x0118, 0x0800000f }, 110 { 0x011c, 0x001800f0 }, 111 }; 112 113 static const u32 pfc_base = 0xe6060000; 114 115 unsigned int i; 116 117 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { 118 writel(~pfc_with_unlock[i].val, pfc_base); 119 writel(pfc_with_unlock[i].val, 120 pfc_base | pfc_with_unlock[i].off); 121 } 122 123 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) 124 writel(pfc_without_unlock[i].val, 125 pfc_base | pfc_without_unlock[i].off); 126} 127 128static void spl_init_gpio(void) 129{ 130 static const u16 gpio_offs[] = { 131 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800 132 }; 133 134 static const struct reg_config gpio_set[] = { 135 { 0x2000, 0x04381000 }, 136 { 0x5000, 0x00000000 }, 137 { 0x5800, 0x000e0000 }, 138 139 }; 140 141 static const struct reg_config gpio_clr[] = { 142 { 0x1000, 0x00000000 }, 143 { 0x2000, 0x04381010 }, 144 { 0x3000, 0x00000000 }, 145 { 0x4000, 0x00000000 }, 146 { 0x5000, 0x00400000 }, 147 { 0x5400, 0x00000000 }, 148 { 0x5800, 0x000e0380 }, 149 }; 150 151 static const u32 gpio_base = 0xe6050000; 152 153 unsigned int i; 154 155 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 156 writel(0, gpio_base | 0x20 | gpio_offs[i]); 157 158 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 159 writel(0, gpio_base | 0x00 | gpio_offs[i]); 160 161 for (i = 0; i < ARRAY_SIZE(gpio_set); i++) 162 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); 163 164 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) 165 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); 166} 167 168static void spl_init_lbsc(void) 169{ 170 static const struct reg_config lbsc_config[] = { 171 { 0x00, 0x00000020 }, 172 { 0x08, 0x00002020 }, 173 { 0x30, 0x2a103320 }, 174 { 0x38, 0xff70ff70 }, 175 }; 176 177 static const u16 lbsc_offs[] = { 178 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 179 }; 180 181 static const u32 lbsc_base = 0xfec00200; 182 183 unsigned int i; 184 185 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { 186 writel(lbsc_config[i].val, 187 lbsc_base | lbsc_config[i].off); 188 writel(lbsc_config[i].val, 189 lbsc_base | (lbsc_config[i].off + 4)); 190 } 191 192 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) 193 writel(0, lbsc_base | lbsc_offs[i]); 194} 195 196static void spl_init_dbsc(void) 197{ 198 static const struct reg_config dbsc_config1[] = { 199 { 0x0018, 0x21000000 }, 200 { 0x0018, 0x11000000 }, 201 { 0x0018, 0x10000000 }, 202 { 0x0280, 0x0000a55a }, 203 { 0x0290, 0x00000010 }, 204 { 0x02a0, 0xf004649b }, 205 { 0x0020, 0x00000007 }, 206 { 0x0024, 0x0f030a02 }, 207 { 0x0030, 0x00000001 }, 208 { 0x00b0, 0x00000000 }, 209 { 0x0040, 0x0000000b }, 210 { 0x0044, 0x00000008 }, 211 { 0x0048, 0x00000000 }, 212 { 0x0050, 0x0000000b }, 213 { 0x0054, 0x000c000b }, 214 { 0x0058, 0x00000027 }, 215 { 0x005c, 0x0000001c }, 216 { 0x0060, 0x00000006 }, 217 { 0x0064, 0x00000020 }, 218 { 0x0068, 0x00000008 }, 219 { 0x006c, 0x0000000c }, 220 { 0x0070, 0x00000009 }, 221 { 0x0074, 0x00000012 }, 222 { 0x0078, 0x000000d0 }, 223 { 0x007c, 0x00140005 }, 224 { 0x0080, 0x00050004 }, 225 { 0x0084, 0x70233005 }, 226 { 0x0088, 0x000c0000 }, 227 { 0x008c, 0x00000300 }, 228 { 0x0090, 0x00000040 }, 229 { 0x0100, 0x00000001 }, 230 { 0x00c0, 0x00020001 }, 231 { 0x00c8, 0x20082008 }, 232 { 0x0380, 0x00020002 }, 233 { 0x0390, 0x0000001f }, 234 }; 235 236 static const struct reg_config dbsc_config5[] = { 237 { 0x0244, 0x00000011 }, 238 { 0x0290, 0x00000006 }, 239 { 0x02a0, 0x0005c000 }, 240 { 0x0290, 0x00000003 }, 241 { 0x02a0, 0x0300c481 }, 242 { 0x0290, 0x00000023 }, 243 { 0x02a0, 0x00fdb6c0 }, 244 { 0x0290, 0x00000011 }, 245 { 0x02a0, 0x1000040b }, 246 { 0x0290, 0x00000012 }, 247 { 0x02a0, 0x9d9cbb66 }, 248 { 0x0290, 0x00000013 }, 249 { 0x02a0, 0x1a868400 }, 250 { 0x0290, 0x00000014 }, 251 { 0x02a0, 0x300214d8 }, 252 { 0x0290, 0x00000015 }, 253 { 0x02a0, 0x00000d70 }, 254 { 0x0290, 0x00000016 }, 255 { 0x02a0, 0x00000006 }, 256 { 0x0290, 0x00000017 }, 257 { 0x02a0, 0x00000018 }, 258 { 0x0290, 0x0000001a }, 259 { 0x02a0, 0x910035c7 }, 260 { 0x0290, 0x00000004 }, 261 }; 262 263 static const struct reg_config dbsc_config6[] = { 264 { 0x0290, 0x00000001 }, 265 { 0x02a0, 0x00000181 }, 266 { 0x0018, 0x11000000 }, 267 { 0x0290, 0x00000004 }, 268 }; 269 270 static const struct reg_config dbsc_config7[] = { 271 { 0x0290, 0x00000001 }, 272 { 0x02a0, 0x0000fe01 }, 273 { 0x0290, 0x00000004 }, 274 }; 275 276 static const struct reg_config dbsc_config8[] = { 277 { 0x0304, 0x00000000 }, 278 { 0x00f4, 0x01004c20 }, 279 { 0x00f8, 0x014000aa }, 280 { 0x00e0, 0x00000140 }, 281 { 0x00e4, 0x00081860 }, 282 { 0x00e8, 0x00010000 }, 283 { 0x0014, 0x00000001 }, 284 { 0x0010, 0x00000001 }, 285 { 0x0280, 0x00000000 }, 286 }; 287 288 static const u32 dbsc3_0_base = DBSC3_0_BASE; 289 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; 290 unsigned int i; 291 292 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) { 293 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); 294 writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off); 295 } 296 297 dbsc_wait(0x240); 298 299 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) { 300 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); 301 writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off); 302 } 303 304 dbsc_wait(0x2a0); 305 306 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) { 307 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); 308 writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off); 309 } 310 311 dbsc_wait(0x2a0); 312 313 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) { 314 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); 315 writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off); 316 } 317 318 dbsc_wait(0x2a0); 319 320 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) { 321 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); 322 writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off); 323 } 324 325} 326 327static void spl_init_qspi(void) 328{ 329 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); 330 331 static const u32 qspi_base = 0xe6b10000; 332 333 writeb(0x08, qspi_base + 0x00); 334 writeb(0x00, qspi_base + 0x01); 335 writeb(0x06, qspi_base + 0x02); 336 writeb(0x01, qspi_base + 0x0a); 337 writeb(0x00, qspi_base + 0x0b); 338 writeb(0x00, qspi_base + 0x0c); 339 writeb(0x00, qspi_base + 0x0d); 340 writeb(0x00, qspi_base + 0x0e); 341 342 writew(0xe080, qspi_base + 0x10); 343 344 writeb(0xc0, qspi_base + 0x18); 345 writeb(0x00, qspi_base + 0x18); 346 writeb(0x00, qspi_base + 0x08); 347 writeb(0x48, qspi_base + 0x00); 348} 349 350void board_init_f(ulong dummy) 351{ 352 int i; 353 354 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 355 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 356 357 /* 358 * SD0 clock is set to 97.5MHz by default. 359 * Set SD2 to the 97.5MHz as well. 360 */ 361 writel(SD_97500KHZ, SD2CKCR); 362 363 spl_init_sys(); 364 spl_init_pfc(); 365 spl_init_gpio(); 366 spl_init_lbsc(); 367 368 /* Unknown, likely ES1.0-specific delay */ 369 for (i = 0; i < 100000; i++) 370 asm volatile("nop"); 371 372 spl_init_dbsc(); 373 spl_init_qspi(); 374} 375 376void spl_board_init(void) 377{ 378 /* UART clocks enabled and gd valid - init serial console */ 379 preloader_console_init(); 380} 381 382void board_boot_order(u32 *spl_boot_list) 383{ 384 const u32 jtag_magic = 0x1337c0de; 385 const u32 load_magic = 0xb33fc0de; 386 387 /* 388 * If JTAG probe sets special word at 0xe6300020, then it must 389 * put U-Boot into RAM and SPL will start it from RAM. 390 */ 391 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { 392 printf("JTAG boot detected!\n"); 393 394 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) 395 ; 396 397 spl_boot_list[0] = BOOT_DEVICE_RAM; 398 spl_boot_list[1] = BOOT_DEVICE_NONE; 399 400 return; 401 } 402 403 /* Boot from SPI NOR with YMODEM UART fallback. */ 404 spl_boot_list[0] = BOOT_DEVICE_SPI; 405 spl_boot_list[1] = BOOT_DEVICE_UART; 406 spl_boot_list[2] = BOOT_DEVICE_NONE; 407} 408 409void reset_cpu(void) 410{ 411} 412