1// SPDX-License-Identifier: GPL-2.0 2/* 3 * board/renesas/gose/gose_spl.c 4 * 5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 6 */ 7 8#include <cpu_func.h> 9#include <init.h> 10#include <malloc.h> 11#include <dm/platform_data/serial_sh.h> 12#include <asm/processor.h> 13#include <asm/mach-types.h> 14#include <asm/io.h> 15#include <linux/bitops.h> 16#include <linux/errno.h> 17#include <asm/arch/sys_proto.h> 18#include <asm/gpio.h> 19#include <asm/arch/renesas.h> 20#include <asm/arch/rcar-mstp.h> 21 22#include <spl.h> 23 24#define TMU0_MSTP125 BIT(25) 25#define SCIF0_MSTP721 BIT(21) 26#define QSPI_MSTP917 BIT(17) 27 28#define SD2CKCR 0xE615026C 29#define SD_97500KHZ 0x7 30 31struct reg_config { 32 u16 off; 33 u32 val; 34}; 35 36static void dbsc_wait(u16 reg) 37{ 38 static const u32 dbsc3_0_base = DBSC3_0_BASE; 39 40 while (!(readl(dbsc3_0_base + reg) & BIT(0))) 41 ; 42} 43 44static void spl_init_sys(void) 45{ 46 u32 r0 = 0; 47 48 writel(0xa5a5a500, 0xe6020004); 49 writel(0xa5a5a500, 0xe6030004); 50 51 asm volatile( 52 /* ICIALLU - Invalidate I$ to PoU */ 53 "mcr 15, 0, %0, cr7, cr5, 0 \n" 54 /* BPIALL - Invalidate branch predictors */ 55 "mcr 15, 0, %0, cr7, cr5, 6 \n" 56 /* Set SCTLR[IZ] */ 57 "mrc 15, 0, %0, cr1, cr0, 0 \n" 58 "orr %0, #0x1800 \n" 59 "mcr 15, 0, %0, cr1, cr0, 0 \n" 60 "isb sy \n" 61 :"=r"(r0)); 62} 63 64static void spl_init_pfc(void) 65{ 66 static const struct reg_config pfc_with_unlock[] = { 67 { 0x0090, 0x60000000 }, 68 { 0x0094, 0x60000000 }, 69 { 0x0098, 0x00800200 }, 70 { 0x009c, 0x00000000 }, 71 { 0x0020, 0x00000000 }, 72 { 0x0024, 0x00000000 }, 73 { 0x0028, 0x000244c8 }, 74 { 0x002c, 0x00000000 }, 75 { 0x0030, 0x00002400 }, 76 { 0x0034, 0x01520000 }, 77 { 0x0038, 0x00724003 }, 78 { 0x003c, 0x00000000 }, 79 { 0x0040, 0x00000000 }, 80 { 0x0044, 0x00000000 }, 81 { 0x0048, 0x00000000 }, 82 { 0x004c, 0x00000000 }, 83 { 0x0050, 0x00000000 }, 84 { 0x0054, 0x00000000 }, 85 { 0x0058, 0x00000000 }, 86 { 0x005c, 0x00000000 }, 87 { 0x0160, 0x00000000 }, 88 { 0x0004, 0xffffffff }, 89 { 0x0008, 0x00ec3fff }, 90 { 0x000c, 0x3bc001e7 }, 91 { 0x0010, 0x5bffffff }, 92 { 0x0014, 0x1ffffffb }, 93 { 0x0018, 0x01bffff0 }, 94 { 0x001c, 0xcf7fffff }, 95 { 0x0074, 0x0381fc00 }, 96 }; 97 98 static const struct reg_config pfc_without_unlock[] = { 99 { 0x0100, 0xffffffdf }, 100 { 0x0104, 0xc883c3ff }, 101 { 0x0108, 0x1201f3c9 }, 102 { 0x010c, 0x00000000 }, 103 { 0x0110, 0xffffeb04 }, 104 { 0x0114, 0xc003ffff }, 105 { 0x0118, 0x0800000f }, 106 { 0x011c, 0x001800f0 }, 107 }; 108 109 static const u32 pfc_base = 0xe6060000; 110 111 unsigned int i; 112 113 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { 114 writel(~pfc_with_unlock[i].val, pfc_base); 115 writel(pfc_with_unlock[i].val, 116 pfc_base | pfc_with_unlock[i].off); 117 } 118 119 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) 120 writel(pfc_without_unlock[i].val, 121 pfc_base | pfc_without_unlock[i].off); 122} 123 124static void spl_init_gpio(void) 125{ 126 static const u16 gpio_offs[] = { 127 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800 128 }; 129 130 static const struct reg_config gpio_set[] = { 131 { 0x2000, 0x04381000 }, 132 { 0x5000, 0x00000000 }, 133 { 0x5800, 0x000e0000 }, 134 }; 135 136 static const struct reg_config gpio_clr[] = { 137 { 0x1000, 0x00000000 }, 138 { 0x2000, 0x04381010 }, 139 { 0x3000, 0x00000000 }, 140 { 0x4000, 0x00000000 }, 141 { 0x5000, 0x00400000 }, 142 { 0x5400, 0x00000000 }, 143 { 0x5800, 0x000e0380 }, 144 }; 145 146 static const u32 gpio_base = 0xe6050000; 147 148 unsigned int i; 149 150 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 151 writel(0, gpio_base | 0x20 | gpio_offs[i]); 152 153 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 154 writel(0, gpio_base | 0x00 | gpio_offs[i]); 155 156 for (i = 0; i < ARRAY_SIZE(gpio_set); i++) 157 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); 158 159 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) 160 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); 161} 162 163static void spl_init_lbsc(void) 164{ 165 static const struct reg_config lbsc_config[] = { 166 { 0x00, 0x00000020 }, 167 { 0x08, 0x00002020 }, 168 { 0x30, 0x2a103320 }, 169 { 0x38, 0xff70ff70 }, 170 }; 171 172 static const u16 lbsc_offs[] = { 173 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 174 }; 175 176 static const u32 lbsc_base = 0xfec00200; 177 178 unsigned int i; 179 180 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { 181 writel(lbsc_config[i].val, 182 lbsc_base | lbsc_config[i].off); 183 writel(lbsc_config[i].val, 184 lbsc_base | (lbsc_config[i].off + 4)); 185 } 186 187 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) 188 writel(0, lbsc_base | lbsc_offs[i]); 189} 190 191static void spl_init_dbsc(void) 192{ 193 static const struct reg_config dbsc_config1[] = { 194 { 0x0280, 0x0000a55a }, 195 { 0x0018, 0x21000000 }, 196 { 0x0018, 0x11000000 }, 197 { 0x0018, 0x10000000 }, 198 { 0x0290, 0x00000001 }, 199 { 0x02a0, 0x80000000 }, 200 { 0x0290, 0x00000004 }, 201 }; 202 203 static const struct reg_config dbsc_config2[] = { 204 { 0x0290, 0x00000006 }, 205 { 0x02a0, 0x0001c000 }, 206 }; 207 208 static const struct reg_config dbsc_config4[] = { 209 { 0x0290, 0x00000010 }, 210 { 0x02a0, 0xf00464db }, 211 { 0x0290, 0x00000061 }, 212 { 0x02a0, 0x0000006d }, 213 { 0x0290, 0x00000001 }, 214 { 0x02a0, 0x00000073 }, 215 { 0x0020, 0x00000007 }, 216 { 0x0024, 0x0f030a02 }, 217 { 0x0030, 0x00000001 }, 218 { 0x00b0, 0x00000000 }, 219 { 0x0040, 0x0000000b }, 220 { 0x0044, 0x00000008 }, 221 { 0x0048, 0x00000000 }, 222 { 0x0050, 0x0000000b }, 223 { 0x0054, 0x000c000b }, 224 { 0x0058, 0x00000027 }, 225 { 0x005c, 0x0000001c }, 226 { 0x0060, 0x00000006 }, 227 { 0x0064, 0x00000020 }, 228 { 0x0068, 0x00000008 }, 229 { 0x006c, 0x0000000c }, 230 { 0x0070, 0x00000009 }, 231 { 0x0074, 0x00000012 }, 232 { 0x0078, 0x000000d0 }, 233 { 0x007c, 0x00140005 }, 234 { 0x0080, 0x00050004 }, 235 { 0x0084, 0x70233005 }, 236 { 0x0088, 0x000c0000 }, 237 { 0x008c, 0x00000200 }, 238 { 0x0090, 0x00000040 }, 239 { 0x0100, 0x00000001 }, 240 { 0x00c0, 0x00020001 }, 241 { 0x00c8, 0x20042004 }, 242 { 0x0380, 0x00020002 }, 243 { 0x0390, 0x0000001f }, 244 }; 245 246 static const struct reg_config dbsc_config5[] = { 247 { 0x0244, 0x00000011 }, 248 { 0x0290, 0x00000003 }, 249 { 0x02a0, 0x0300c561 }, 250 { 0x0290, 0x00000023 }, 251 { 0x02a0, 0x00fcdb60 }, 252 { 0x0290, 0x00000011 }, 253 { 0x02a0, 0x1000040b }, 254 { 0x0290, 0x00000012 }, 255 { 0x02a0, 0x9d9cbb66 }, 256 { 0x0290, 0x00000013 }, 257 { 0x02a0, 0x1a868400 }, 258 { 0x0290, 0x00000014 }, 259 { 0x02a0, 0x300214d8 }, 260 { 0x0290, 0x00000015 }, 261 { 0x02a0, 0x00000d70 }, 262 { 0x0290, 0x00000016 }, 263 { 0x02a0, 0x00000006 }, 264 { 0x0290, 0x00000017 }, 265 { 0x02a0, 0x00000018 }, 266 { 0x0290, 0x0000001a }, 267 { 0x02a0, 0x910035c7 }, 268 { 0x0290, 0x00000004 }, 269 }; 270 271 static const struct reg_config dbsc_config6[] = { 272 { 0x0290, 0x00000001 }, 273 { 0x02a0, 0x00000181 }, 274 { 0x0018, 0x11000000 }, 275 { 0x0290, 0x00000004 }, 276 }; 277 278 static const struct reg_config dbsc_config7[] = { 279 { 0x0290, 0x00000001 }, 280 { 0x02a0, 0x0000fe01 }, 281 { 0x0304, 0x00000000 }, 282 { 0x00f4, 0x01004c20 }, 283 { 0x00f8, 0x014000aa }, 284 { 0x00e0, 0x00000140 }, 285 { 0x00e4, 0x00081860 }, 286 { 0x00e8, 0x00010000 }, 287 { 0x0290, 0x00000004 }, 288 }; 289 290 static const struct reg_config dbsc_config8[] = { 291 { 0x0014, 0x00000001 }, 292 { 0x0010, 0x00000001 }, 293 { 0x0280, 0x00000000 }, 294 }; 295 296 static const u32 dbsc3_0_base = DBSC3_0_BASE; 297 unsigned int i; 298 299 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) 300 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); 301 302 dbsc_wait(0x2a0); 303 304 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) 305 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); 306 307 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) 308 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); 309 310 dbsc_wait(0x240); 311 312 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) 313 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); 314 315 dbsc_wait(0x2a0); 316 317 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) 318 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); 319 320 dbsc_wait(0x2a0); 321 322 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) 323 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); 324 325 dbsc_wait(0x2a0); 326 327 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) 328 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); 329 330} 331 332static void spl_init_qspi(void) 333{ 334 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); 335 336 static const u32 qspi_base = 0xe6b10000; 337 338 writeb(0x08, qspi_base + 0x00); 339 writeb(0x00, qspi_base + 0x01); 340 writeb(0x06, qspi_base + 0x02); 341 writeb(0x01, qspi_base + 0x0a); 342 writeb(0x00, qspi_base + 0x0b); 343 writeb(0x00, qspi_base + 0x0c); 344 writeb(0x00, qspi_base + 0x0d); 345 writeb(0x00, qspi_base + 0x0e); 346 347 writew(0xe080, qspi_base + 0x10); 348 349 writeb(0xc0, qspi_base + 0x18); 350 writeb(0x00, qspi_base + 0x18); 351 writeb(0x00, qspi_base + 0x08); 352 writeb(0x48, qspi_base + 0x00); 353} 354 355void board_init_f(ulong dummy) 356{ 357 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 358 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 359 360 /* 361 * SD0 clock is set to 97.5MHz by default. 362 * Set SD2 to the 97.5MHz as well. 363 */ 364 writel(SD_97500KHZ, SD2CKCR); 365 366 spl_init_sys(); 367 spl_init_pfc(); 368 spl_init_gpio(); 369 spl_init_lbsc(); 370 spl_init_dbsc(); 371 spl_init_qspi(); 372} 373 374void spl_board_init(void) 375{ 376 /* UART clocks enabled and gd valid - init serial console */ 377 preloader_console_init(); 378} 379 380void board_boot_order(u32 *spl_boot_list) 381{ 382 const u32 jtag_magic = 0x1337c0de; 383 const u32 load_magic = 0xb33fc0de; 384 385 /* 386 * If JTAG probe sets special word at 0xe6300020, then it must 387 * put U-Boot into RAM and SPL will start it from RAM. 388 */ 389 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { 390 printf("JTAG boot detected!\n"); 391 392 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) 393 ; 394 395 spl_boot_list[0] = BOOT_DEVICE_RAM; 396 spl_boot_list[1] = BOOT_DEVICE_NONE; 397 398 return; 399 } 400 401 /* Boot from SPI NOR with YMODEM UART fallback. */ 402 spl_boot_list[0] = BOOT_DEVICE_SPI; 403 spl_boot_list[1] = BOOT_DEVICE_UART; 404 spl_boot_list[2] = BOOT_DEVICE_NONE; 405} 406 407void reset_cpu(void) 408{ 409} 410