1274880Sbapt# SPDX-License-Identifier: GPL-2.0+ 2241675Suqs# 3241675Suqs# Copyright (C) 2011-2012 4274880Sbapt# Gerald Kerma <dreagle@doukki.net> 5241675Suqs# Simon Baatz <gmbnomis@gmail.com> 6241675Suqs# Luka Perkov <luka@openwrt.org> 7241675Suqs# Refer doc/README.kwbimage for more details about how-to configure 8241675Suqs# and create kirkwood boot image 9241675Suqs# 10241675Suqs 11241675Suqs# Boot Media configurations 12241675SuqsBOOT_FROM nand 13241675SuqsNAND_ECC_MODE default 14241675SuqsNAND_PAGE_SIZE 0x0800 15241675Suqs 16241675Suqs# SOC registers configuration using bootrom header extension 17241675Suqs# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 18241675Suqs 19241675Suqs# Configure RGMII-0 interface pad voltage to 1.8V 20241675SuqsDATA 0xffd100e0 0x1b1b1b9b 21241675Suqs 22241675Suqs# Dram initalization for SINGLE x16 CL=5 @ 400MHz 23241675SuqsDATA 0xffd01400 0x43000c30 # DDR Configuration register 24241675Suqs# bit13-0: 0xc30, (3120 DDR2 clks refresh rate) 25241675Suqs# bit23-14: 0x0, 26241675Suqs# bit24: 0x1, enable exit self refresh mode on DDR access 27241675Suqs# bit25: 0x1, required 28241675Suqs# bit29-26: 0x0, 29241675Suqs# bit31-30: 0x1, 30241675Suqs 31241675SuqsDATA 0xffd01404 0x37543000 # DDR Controller Control Low 32241675Suqs# bit4: 0x0, addr/cmd in smame cycle 33241675Suqs# bit5: 0x0, clk is driven during self refresh, we don't care for APX 34261344Suqs# bit6: 0x0, use recommended falling edge of clk for addr/cmd 35274880Sbapt# bit14: 0x0, input buffer always powered up 36241675Suqs# bit18: 0x1, cpu lock transaction enabled 37241675Suqs# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 38241675Suqs# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 39274880Sbapt# bit30-28: 0x3, required 40241675Suqs# bit31: 0x0, no additional STARTBURST delay 41274880Sbapt 42274880SbaptDATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 43241675Suqs# bit3-0: TRAS lsbs 44241675Suqs# bit7-4: TRCD 45241675Suqs# bit11-8: TRP 46241675Suqs# bit15-12: TWR 47241675Suqs# bit19-16: TWTR 48241675Suqs# bit20: TRAS msb 49241675Suqs# bit23-21: 0x0 50241675Suqs# bit27-24: TRRD 51241675Suqs# bit31-28: TRTP 52241675Suqs 53241675SuqsDATA 0xffd0140c 0x00000a33 # DDR Timing (High) 54241675Suqs# bit6-0: TRFC 55241675Suqs# bit8-7: TR2R 56241675Suqs# bit10-9: TR2W 57241675Suqs# bit12-11: TW2W 58241675Suqs# bit31-13: 0x0, required 59241675Suqs 60241675SuqsDATA 0xffd01410 0x0000000c # DDR Address Control 61241675Suqs# bit1-0: 00, Cs0width (x8) 62241675Suqs# bit3-2: 11, Cs0size (1Gb) 63241675Suqs# bit5-4: 00, Cs1width (x8) 64241675Suqs# bit7-6: 11, Cs1size (1Gb) 65241675Suqs# bit9-8: 00, Cs2width (nonexistent) 66241675Suqs# bit11-10: 00, Cs2size (nonexistent) 67241675Suqs# bit13-12: 00, Cs3width (nonexistent) 68241675Suqs# bit15-14: 00, Cs3size (nonexistent) 69274880Sbapt# bit16: 0, Cs0AddrSel 70241675Suqs# bit17: 0, Cs1AddrSel 71241675Suqs# bit18: 0, Cs2AddrSel 72241675Suqs# bit19: 0, Cs3AddrSel 73241675Suqs# bit31-20: 0x0, required 74241675Suqs 75241675SuqsDATA 0xffd01414 0x00000000 # DDR Open Pages Control 76241675Suqs# bit0: 0, OpenPage enabled 77241675Suqs# bit31-1: 0x0, required 78241675Suqs 79241675SuqsDATA 0xffd01418 0x00000000 # DDR Operation 80241675Suqs# bit3-0: 0x0, DDR cmd 81241675Suqs# bit31-4: 0x0, required 82241675Suqs 83241675SuqsDATA 0xffd0141c 0x00000c52 # DDR Mode 84241675Suqs# bit2-0: 0x2, BurstLen=2 required 85241675Suqs# bit3: 0x0, BurstType=0 required 86241675Suqs# bit6-4: 0x4, CL=5 87241675Suqs# bit7: 0x0, TestMode=0 normal 88241675Suqs# bit8: 0x0, DLL reset=0 normal 89241675Suqs# bit11-9: 0x6, auto-precharge write recovery 90241675Suqs# bit12: 0x0, PD must be zero 91241675Suqs# bit31-13: 0x0, required 92241675Suqs 93241675SuqsDATA 0xffd01420 0x00000040 # DDR Extended Mode 94241675Suqs# bit0: 0, DDR DLL enabled 95241675Suqs# bit1: 0, DDR drive strenght normal 96241675Suqs# bit2: 1, DDR ODT control lsd (disabled) 97241675Suqs# bit5-3: 0x0, required 98241675Suqs# bit6: 0, DDR ODT control msb, (disabled) 99261344Suqs# bit9-7: 0x0, required 100241675Suqs# bit10: 0, differential DQS enabled 101261344Suqs# bit11: 0, required 102261344Suqs# bit12: 0, DDR output buffer enabled 103241675Suqs# bit31-13: 0x0, required 104241675Suqs 105241675SuqsDATA 0xffd01424 0x0000f17f # DDR Controller Control High 106241675Suqs# bit2-0: 0x7, required 107241675Suqs# bit3: 0x1, MBUS Burst Chop disabled 108274880Sbapt# bit6-4: 0x7, required 109274880Sbapt# bit7: 0x0, 110241675Suqs# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz 111274880Sbapt# bit9: 0x0, no half clock cycle addition to dataout 112241675Suqs# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals 113241675Suqs# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh 114241675Suqs# bit15-12: 0xf, required 115241675Suqs# bit31-16: 0, required 116241675Suqs 117241675SuqsDATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) 118241675SuqsDATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) 119241675Suqs 120274880SbaptDATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 121241675SuqsDATA 0xffd01504 0x0ffffff1 # CS[0]n Size 122274880Sbapt# bit0: 0x1, Window enabled 123241675Suqs# bit1: 0x0, Write Protect disabled 124241675Suqs# bit3-2: 0x0, CS0 hit selected 125274880Sbapt# bit23-4: 0xfffff, required 126241675Suqs# bit31-24: 0x0f, Size (i.e. 256MB) 127241675Suqs 128241675SuqsDATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb 129241675SuqsDATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled 130261344Suqs 131274880SbaptDATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled 132241675SuqsDATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled 133241675Suqs 134241675SuqsDATA 0xffd01494 0x00030000 # DDR ODT Control (Low) 135241675Suqs# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1 136241675Suqs# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0 137241675Suqs# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 138241675Suqs# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 139241675Suqs 140261344SuqsDATA 0xffd01498 0x00000000 # DDR ODT Control (High) 141241675Suqs# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above 142261344Suqs# bit3-2: 0x1, ODT1 active NEVER! 143261344Suqs# bit31-4: 0x0, required 144241675Suqs 145241675SuqsDATA 0xffd0149c 0x0000e803 # CPU ODT Control 146261344SuqsDATA 0xffd01480 0x00000001 # DDR Initialization Control 147241675Suqs# bit0: 0x1, enable DDR init upon this register write 148274880Sbapt 149241675SuqsDATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register 150241675SuqsDATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register 151241675Suqs 152241675Suqs# End of Header extension 153241675SuqsDATA 0x0 0x0 154241675Suqs