1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018 NXP 4 * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com> 5 */ 6 7#include <common.h> 8#include <env.h> 9#include <init.h> 10#include <malloc.h> 11#include <errno.h> 12#include <asm/global_data.h> 13#include <asm/io.h> 14#include <miiphy.h> 15#include <netdev.h> 16#include <asm/mach-imx/iomux-v3.h> 17#include <asm-generic/gpio.h> 18#include <fsl_esdhc_imx.h> 19#include <mmc.h> 20#include <asm/arch/imx8mq_pins.h> 21#include <asm/arch/sys_proto.h> 22#include <asm/mach-imx/gpio.h> 23#include <asm/mach-imx/mxc_i2c.h> 24#include <asm/arch/clock.h> 25#include <spl.h> 26#include <linux/bitops.h> 27#include <linux/delay.h> 28#include <power/pmic.h> 29 30DECLARE_GLOBAL_DATA_PTR; 31 32 33#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 34 35static iomux_v3_cfg_t const wdog_pads[] = { 36 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), 37}; 38 39 40int board_early_init_f(void) 41{ 42 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 43 44 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 45 set_wdog_reset(wdog); 46 47 return 0; 48} 49 50#ifdef CONFIG_FEC_MXC 51 52#define PHY_RESET IMX_GPIO_NR(1, 9) 53#define PHY_RX_CTL IMX_GPIO_NR(1, 24) 54#define PHY_RXC IMX_GPIO_NR(1, 25) 55#define PHY_RD0 IMX_GPIO_NR(1, 26) 56#define PHY_RD1 IMX_GPIO_NR(1, 27) 57#define PHY_RD2 IMX_GPIO_NR(1, 28) 58#define PHY_RD3 IMX_GPIO_NR(1, 29) 59 60#define STRAP_AR8035 (0x28) // 0010 1000 61 62static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = { 63 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6), 64 IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91), 65 IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91), 66 IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91), 67 IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1), 68 IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91), 69 /* 1.8V(1)/1.5V select(0) */ 70 IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1), 71}; 72 73static const iomux_v3_cfg_t enet_ar8035_pads[] = { 74 IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91), 75 IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91), 76 IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91), 77 IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91), 78 IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91), 79 IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91), 80}; 81 82static void setup_fec(void) 83{ 84 struct iomuxc_gpr_base_regs *gpr = 85 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 86 87 /* Pull PHY into reset */ 88 gpio_request(PHY_RESET, "fec_rst"); 89 gpio_direction_output(PHY_RESET, 0); 90 91 /* Configure ethernet pins value as GPIOs */ 92 gpio_request(PHY_RD0, "fec_rd0"); 93 gpio_direction_output(PHY_RD0, 0); 94 gpio_request(PHY_RD1, "fec_rd1"); 95 gpio_direction_output(PHY_RD1, 0); 96 gpio_request(PHY_RD2, "fec_rd2"); 97 gpio_direction_output(PHY_RD2, 0); 98 gpio_request(PHY_RD3, "fec_rd3"); 99 gpio_direction_output(PHY_RD3, 1); 100 gpio_request(PHY_RX_CTL, "fec_rx_ctl"); 101 gpio_direction_output(PHY_RX_CTL, 0); 102 gpio_request(PHY_RXC, "fec_rxc"); 103 gpio_direction_output(PHY_RXC, 1); 104 105 /* Set ethernet pins to GPIO to bootstrap PHY */ 106 imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads, 107 ARRAY_SIZE(enet_ar8035_gpio_pads)); 108 109 /* Use 125M anatop REF_CLK1 for ENET1, not from external */ 110 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); 111 /* Enable RGMII TX clk output */ 112 setbits_le32(&gpr->gpr[1], BIT(22)); 113 set_clk_enet(ENET_125MHZ); 114 115 /* 1 ms minimum reset pulse for ar8035 */ 116 mdelay(1); 117 118 /* Release PHY from reset */ 119 gpio_set_value(PHY_RESET, 1); 120 121 /* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */ 122 udelay(12); 123 124 /* Change ethernet pins back to normal function */ 125 imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads, 126 ARRAY_SIZE(enet_ar8035_pads)); 127} 128#endif 129 130#define USB1_HUB_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 131#define USB1_HUB_RESET IMX_GPIO_NR(1, 14) 132 133static void setup_usb(void) 134{ 135 imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 | 136 MUX_PAD_CTRL(USB1_HUB_PAD_CTRL)); 137 gpio_request(USB1_HUB_RESET, "usb1_rst"); 138 gpio_direction_output(USB1_HUB_RESET, 0); 139 mdelay(10); 140 gpio_set_value(USB1_HUB_RESET, 1); 141} 142 143int board_init(void) 144{ 145#ifdef CONFIG_FEC_MXC 146 setup_fec(); 147#endif 148 149 setup_usb(); 150 151#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3) 152 init_usb_clk(); 153#endif 154 155 return 0; 156} 157 158int board_mmc_get_env_dev(int devno) 159{ 160 return devno; 161} 162 163int board_late_init(void) 164{ 165#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 166 env_set("board_name", "Reform2"); 167 env_set("board_rev", "iMX8MQ"); 168#endif 169 170 return 0; 171} 172