1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
4 * Copyright (C) 2009-2012
5 * Wojciech Dubowik <wojciech.dubowik@neratec.com>
6 * Luka Perkov <luka@openwrt.org>
7 */
8
9#include <common.h>
10#include <init.h>
11#include <netdev.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/soc.h>
14#include <asm/arch/mpp.h>
15#include <asm/global_data.h>
16#include <linux/bitops.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20#define ICONNECT_OE_LOW                 (~BIT(7))
21#define ICONNECT_OE_HIGH                (~BIT(10))
22#define ICONNECT_OE_VAL_LOW             (0)
23#define ICONNECT_OE_VAL_HIGH            BIT(10)
24
25int board_early_init_f(void)
26{
27	/*
28	 * default gpio configuration
29	 * There are maximum 64 gpios controlled through 2 sets of registers
30	 * the below configuration configures mainly initial LED status
31	 */
32	mvebu_config_gpio(ICONNECT_OE_VAL_LOW,
33			  ICONNECT_OE_VAL_HIGH,
34			  ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
35
36	/* Multi-Purpose Pins Functionality configuration */
37	static const u32 kwmpp_config[] = {
38		MPP0_NF_IO2,
39		MPP1_NF_IO3,
40		MPP2_NF_IO4,
41		MPP3_NF_IO5,
42		MPP4_NF_IO6,
43		MPP5_NF_IO7,
44		MPP6_SYSRST_OUTn,	/* Reset signal */
45		MPP7_GPO,
46		MPP8_TW_SDA,		/* I2C */
47		MPP9_TW_SCK,		/* I2C */
48		MPP10_UART0_TXD,
49		MPP11_UART0_RXD,
50		MPP12_GPO,		/* Reset button */
51		MPP13_SD_CMD,
52		MPP14_SD_D0,
53		MPP15_SD_D1,
54		MPP16_SD_D2,
55		MPP17_SD_D3,
56		MPP18_NF_IO0,
57		MPP19_NF_IO1,
58		MPP20_GE1_0,
59		MPP21_GE1_1,
60		MPP22_GE1_2,
61		MPP23_GE1_3,
62		MPP24_GE1_4,
63		MPP25_GE1_5,
64		MPP26_GE1_6,
65		MPP27_GE1_7,
66		MPP28_GPIO,
67		MPP29_GPIO,
68		MPP30_GE1_10,
69		MPP31_GE1_11,
70		MPP32_GE1_12,
71		MPP33_GE1_13,
72		MPP34_GE1_14,
73		MPP35_GPIO,		/* OTB button */
74		MPP36_AUDIO_SPDIFI,
75		MPP37_AUDIO_SPDIFO,
76		MPP38_GPIO,
77		MPP39_TDM_SPI_CS0,
78		MPP40_TDM_SPI_SCK,
79		MPP41_GPIO,		/* LED brightness */
80		MPP42_GPIO,		/* LED power (blue) */
81		MPP43_GPIO,		/* LED power (red) */
82		MPP44_GPIO,		/* LED USB 1 */
83		MPP45_GPIO,		/* LED USB 2 */
84		MPP46_GPIO,		/* LED USB 3 */
85		MPP47_GPIO,		/* LED USB 4 */
86		MPP48_GPIO,		/* LED OTB */
87		MPP49_GPIO,
88		0
89	};
90	kirkwood_mpp_conf(kwmpp_config, NULL);
91	return 0;
92}
93
94int board_eth_init(struct bd_info *bis)
95{
96	return cpu_eth_init(bis);
97}
98
99int board_init(void)
100{
101	/* address of boot parameters */
102	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
103
104	return 0;
105}
106
107int board_late_init(void)
108{
109	/* Do late init to ensure successful enumeration of PCIe devices */
110	pci_init();
111	return 0;
112}
113