1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2014 4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 5 */ 6 7#ifdef CONFIG_GDSYS_LEGACY_DRIVERS 8 9#include <common.h> 10 11#include <gdsys_fpga.h> 12#include <linux/bitops.h> 13 14enum pcb_video_type { 15 PCB_DVI_SL, 16 PCB_DP_165MPIX, 17 PCB_DP_300MPIX, 18 PCB_HDMI, 19 PCB_DP_1_2, 20 PCB_HDMI_2_0, 21}; 22 23enum pcb_transmission_type { 24 PCB_CAT_1G, 25 PCB_FIBER_3G, 26 PCB_CAT_10G, 27 PCB_FIBER_10G, 28}; 29 30enum carrier_speed { 31 CARRIER_SPEED_1G, 32 CARRIER_SPEED_3G, 33 CARRIER_SPEED_2_5G = CARRIER_SPEED_3G, 34 CARRIER_SPEED_10G, 35}; 36 37enum ram_config { 38 RAM_DDR2_32BIT_295MBPS, 39 RAM_DDR3_32BIT_590MBPS, 40 RAM_DDR3_48BIT_590MBPS, 41 RAM_DDR3_64BIT_1800MBPS, 42 RAM_DDR3_48BIT_1800MBPS, 43}; 44 45enum sysclock { 46 SYSCLK_147456, 47}; 48 49struct fpga_versions { 50 bool video_channel; 51 bool con_side; 52 enum pcb_video_type pcb_video_type; 53 enum pcb_transmission_type pcb_transmission_type; 54 unsigned int hw_version; 55}; 56 57struct fpga_features { 58 u8 video_channels; 59 u8 carriers; 60 enum carrier_speed carrier_speed; 61 enum ram_config ram_config; 62 enum sysclock sysclock; 63 64 bool pcm_tx; 65 bool pcm_rx; 66 bool spdif_tx; 67 bool spdif_rx; 68 bool usb2; 69 bool rs232; 70 bool compression_type1; 71 bool compression_type2; 72 bool compression_type3; 73 bool interlace; 74 bool osd; 75 bool compression_pipes; 76}; 77 78#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM 79 80static int get_versions(unsigned int fpga, struct fpga_versions *versions) 81{ 82 enum { 83 VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12), 84 VERSIONS_FPGA_CON_SIDE = BIT(13), 85 VERSIONS_FPGA_SC = BIT(14), 86 VERSIONS_PCB_CON = BIT(9), 87 VERSIONS_PCB_SC = BIT(8), 88 VERSIONS_PCB_VIDEO_MASK = 0x3 << 6, 89 VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6, 90 VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6, 91 VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4, 92 VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4, 93 VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4, 94 VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4, 95 VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4, 96 VERSIONS_HW_VER_MASK = 0xf << 0, 97 }; 98 u16 raw_versions; 99 100 memset(versions, 0, sizeof(struct fpga_versions)); 101 102 FPGA_GET_REG(fpga, versions, &raw_versions); 103 104 versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL; 105 versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE; 106 107 switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) { 108 case VERSIONS_PCB_VIDEO_DP_1_2: 109 versions->pcb_video_type = PCB_DP_1_2; 110 break; 111 112 case VERSIONS_PCB_VIDEO_HDMI_2_0: 113 versions->pcb_video_type = PCB_HDMI_2_0; 114 break; 115 } 116 117 switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) { 118 case VERSIONS_PCB_TRANSMISSION_FIBER_10G: 119 versions->pcb_transmission_type = PCB_FIBER_10G; 120 break; 121 122 case VERSIONS_PCB_TRANSMISSION_CAT_10G: 123 versions->pcb_transmission_type = PCB_CAT_10G; 124 break; 125 126 case VERSIONS_PCB_TRANSMISSION_FIBER_3G: 127 versions->pcb_transmission_type = PCB_FIBER_3G; 128 break; 129 130 case VERSIONS_PCB_TRANSMISSION_CAT_1G: 131 versions->pcb_transmission_type = PCB_CAT_1G; 132 break; 133 134 } 135 136 versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; 137 138 return 0; 139} 140 141static int get_features(unsigned int fpga, struct fpga_features *features) 142{ 143 enum { 144 FEATURE_SPDIF_RX = BIT(15), 145 FEATURE_SPDIF_TX = BIT(14), 146 FEATURE_PCM_RX = BIT(13), 147 FEATURE_PCM_TX = BIT(12), 148 FEATURE_RAM_MASK = GENMASK(11, 8), 149 FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8, 150 FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8, 151 FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8, 152 FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8, 153 FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8, 154 FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6), 155 FEATURE_CARRIER_SPEED_1G = 0x0 << 6, 156 FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6, 157 FEATURE_CARRIER_SPEED_10G = 0x2 << 6, 158 FEATURE_CARRIERS_MASK = GENMASK(5, 4), 159 FEATURE_CARRIERS_0 = 0x0 << 4, 160 FEATURE_CARRIERS_1 = 0x1 << 4, 161 FEATURE_CARRIERS_2 = 0x2 << 4, 162 FEATURE_CARRIERS_4 = 0x3 << 4, 163 FEATURE_USB2 = BIT(3), 164 FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0), 165 FEATURE_VIDEOCHANNELS_0 = 0x0 << 0, 166 FEATURE_VIDEOCHANNELS_1 = 0x1 << 0, 167 FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0, 168 FEATURE_VIDEOCHANNELS_2 = 0x3 << 0, 169 }; 170 171 enum { 172 EXT_FEATURE_OSD = BIT(15), 173 EXT_FEATURE_ETHERNET = BIT(9), 174 EXT_FEATURE_INTERLACE = BIT(8), 175 EXT_FEATURE_RS232 = BIT(7), 176 EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4), 177 EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4, 178 EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4, 179 EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4, 180 EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0), 181 EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1), 182 EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2), 183 }; 184 185 u16 raw_features; 186 u16 raw_extended_features; 187 188 memset(features, 0, sizeof(struct fpga_features)); 189 190 FPGA_GET_REG(fpga, fpga_features, &raw_features); 191 FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); 192 193 switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) { 194 case FEATURE_VIDEOCHANNELS_0: 195 features->video_channels = 0; 196 break; 197 198 case FEATURE_VIDEOCHANNELS_1: 199 features->video_channels = 1; 200 break; 201 202 case FEATURE_VIDEOCHANNELS_1_1: 203 case FEATURE_VIDEOCHANNELS_2: 204 features->video_channels = 2; 205 break; 206 }; 207 208 switch (raw_features & FEATURE_CARRIERS_MASK) { 209 case FEATURE_CARRIERS_0: 210 features->carriers = 0; 211 break; 212 213 case FEATURE_CARRIERS_1: 214 features->carriers = 1; 215 break; 216 217 case FEATURE_CARRIERS_2: 218 features->carriers = 2; 219 break; 220 221 case FEATURE_CARRIERS_4: 222 features->carriers = 4; 223 break; 224 } 225 226 switch (raw_features & FEATURE_CARRIER_SPEED_MASK) { 227 case FEATURE_CARRIER_SPEED_1G: 228 features->carrier_speed = CARRIER_SPEED_1G; 229 break; 230 case FEATURE_CARRIER_SPEED_2_5G: 231 features->carrier_speed = CARRIER_SPEED_2_5G; 232 break; 233 case FEATURE_CARRIER_SPEED_10G: 234 features->carrier_speed = CARRIER_SPEED_10G; 235 break; 236 } 237 238 switch (raw_features & FEATURE_RAM_MASK) { 239 case FEATURE_RAM_DDR2_32BIT_295MBPS: 240 features->ram_config = RAM_DDR2_32BIT_295MBPS; 241 break; 242 243 case FEATURE_RAM_DDR3_32BIT_590MBPS: 244 features->ram_config = RAM_DDR3_32BIT_590MBPS; 245 break; 246 247 case FEATURE_RAM_DDR3_48BIT_590MBPS: 248 features->ram_config = RAM_DDR3_48BIT_590MBPS; 249 break; 250 251 case FEATURE_RAM_DDR3_64BIT_1800MBPS: 252 features->ram_config = RAM_DDR3_64BIT_1800MBPS; 253 break; 254 255 case FEATURE_RAM_DDR3_48BIT_1800MBPS: 256 features->ram_config = RAM_DDR3_48BIT_1800MBPS; 257 break; 258 } 259 260 features->pcm_tx = raw_features & FEATURE_PCM_TX; 261 features->pcm_rx = raw_features & FEATURE_PCM_RX; 262 features->spdif_tx = raw_features & FEATURE_SPDIF_TX; 263 features->spdif_rx = raw_features & FEATURE_SPDIF_RX; 264 features->usb2 = raw_features & FEATURE_USB2; 265 features->rs232 = raw_extended_features & EXT_FEATURE_RS232; 266 features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1; 267 features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2; 268 features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3; 269 features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE; 270 features->osd = raw_extended_features & EXT_FEATURE_OSD; 271 features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK; 272 273 return 0; 274} 275 276#else 277 278static int get_versions(unsigned int fpga, struct fpga_versions *versions) 279{ 280 enum { 281 /* HW version encoding is a mess, leave it for the moment */ 282 VERSIONS_HW_VER_MASK = 0xf << 0, 283 VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4), 284 VERSIONS_SFP = BIT(5), 285 VERSIONS_VIDEO_MASK = 0x7 << 6, 286 VERSIONS_VIDEO_DVI = 0x0 << 6, 287 VERSIONS_VIDEO_DP_165 = 0x1 << 6, 288 VERSIONS_VIDEO_DP_300 = 0x2 << 6, 289 VERSIONS_VIDEO_HDMI = 0x3 << 6, 290 VERSIONS_UT_MASK = 0xf << 12, 291 VERSIONS_UT_MAIN_SERVER = 0x0 << 12, 292 VERSIONS_UT_MAIN_USER = 0x1 << 12, 293 VERSIONS_UT_VIDEO_SERVER = 0x2 << 12, 294 VERSIONS_UT_VIDEO_USER = 0x3 << 12, 295 }; 296 u16 raw_versions; 297 298 memset(versions, 0, sizeof(struct fpga_versions)); 299 300 FPGA_GET_REG(fpga, versions, &raw_versions); 301 302 switch (raw_versions & VERSIONS_UT_MASK) { 303 case VERSIONS_UT_MAIN_SERVER: 304 versions->video_channel = false; 305 versions->con_side = false; 306 break; 307 308 case VERSIONS_UT_MAIN_USER: 309 versions->video_channel = false; 310 versions->con_side = true; 311 break; 312 313 case VERSIONS_UT_VIDEO_SERVER: 314 versions->video_channel = true; 315 versions->con_side = false; 316 break; 317 318 case VERSIONS_UT_VIDEO_USER: 319 versions->video_channel = true; 320 versions->con_side = true; 321 break; 322 323 } 324 325 switch (raw_versions & VERSIONS_VIDEO_MASK) { 326 case VERSIONS_VIDEO_DVI: 327 versions->pcb_video_type = PCB_DVI_SL; 328 break; 329 330 case VERSIONS_VIDEO_DP_165: 331 versions->pcb_video_type = PCB_DP_165MPIX; 332 break; 333 334 case VERSIONS_VIDEO_DP_300: 335 versions->pcb_video_type = PCB_DP_300MPIX; 336 break; 337 338 case VERSIONS_VIDEO_HDMI: 339 versions->pcb_video_type = PCB_HDMI; 340 break; 341 } 342 343 versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; 344 345 if (raw_versions & VERSIONS_SFP) 346 versions->pcb_transmission_type = PCB_FIBER_3G; 347 else 348 versions->pcb_transmission_type = PCB_CAT_1G; 349 350 return 0; 351} 352 353static int get_features(unsigned int fpga, struct fpga_features *features) 354{ 355 enum { 356 FEATURE_CARRIER_SPEED_2_5 = BIT(4), 357 FEATURE_RAM_MASK = 0x7 << 5, 358 FEATURE_RAM_DDR2_32BIT = 0x0 << 5, 359 FEATURE_RAM_DDR3_32BIT = 0x1 << 5, 360 FEATURE_RAM_DDR3_48BIT = 0x2 << 5, 361 FEATURE_PCM_AUDIO_TX = BIT(9), 362 FEATURE_PCM_AUDIO_RX = BIT(10), 363 FEATURE_OSD = BIT(11), 364 FEATURE_USB20 = BIT(12), 365 FEATURE_COMPRESSION_MASK = 7 << 13, 366 FEATURE_COMPRESSION_TYPE1 = 0x1 << 13, 367 FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13, 368 FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13, 369 }; 370 371 enum { 372 EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0), 373 EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1), 374 EXTENDED_FEATURE_RS232 = BIT(2), 375 EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3), 376 EXTENDED_FEATURE_INTERLACE = BIT(4), 377 }; 378 379 u16 raw_features; 380#ifdef GDSYS_LEGACY_DRIVERS 381 u16 raw_extended_features; 382#endif 383 384 memset(features, 0, sizeof(struct fpga_features)); 385 386 FPGA_GET_REG(fpga, fpga_features, &raw_features); 387#ifdef GDSYS_LEGACY_DRIVERS 388 FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); 389#endif 390 391 features->video_channels = raw_features & 0x3; 392 features->carriers = (raw_features >> 2) & 0x3; 393 394 features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5) 395 ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G; 396 397 switch (raw_features & FEATURE_RAM_MASK) { 398 case FEATURE_RAM_DDR2_32BIT: 399 features->ram_config = RAM_DDR2_32BIT_295MBPS; 400 break; 401 402 case FEATURE_RAM_DDR3_32BIT: 403 features->ram_config = RAM_DDR3_32BIT_590MBPS; 404 break; 405 406 case FEATURE_RAM_DDR3_48BIT: 407 features->ram_config = RAM_DDR3_48BIT_590MBPS; 408 break; 409 } 410 411 features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX; 412 features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX; 413#ifdef GDSYS_LEGACY_DRIVERS 414 features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX; 415 features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX; 416#endif 417 418 features->usb2 = raw_features & FEATURE_USB20; 419#ifdef GDSYS_LEGACY_DRIVERS 420 features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232; 421#endif 422 423 features->compression_type1 = false; 424 features->compression_type2 = false; 425 features->compression_type3 = false; 426 switch (raw_features & FEATURE_COMPRESSION_MASK) { 427 case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3: 428 features->compression_type3 = true; 429 case FEATURE_COMPRESSION_TYPE1_TYPE2: 430 features->compression_type2 = true; 431 case FEATURE_COMPRESSION_TYPE1: 432 features->compression_type1 = true; 433 break; 434 } 435 436#ifdef GDSYS_LEGACY_DRIVERS 437 features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE; 438#endif 439 features->osd = raw_features & FEATURE_OSD; 440#ifdef GDSYS_LEGACY_DRIVERS 441 features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES; 442#endif 443 444 return 0; 445} 446 447#include <linux/bitops.h> 448#endif 449 450bool ioep_fpga_has_osd(unsigned int fpga) 451{ 452 struct fpga_features features; 453 454 get_features(fpga, &features); 455 456 return features.osd; 457} 458 459void ioep_fpga_print_info(unsigned int fpga) 460{ 461 u16 fpga_version; 462 struct fpga_versions versions; 463 struct fpga_features features; 464 465 FPGA_GET_REG(fpga, fpga_version, &fpga_version); 466 get_versions(fpga, &versions); 467 get_features(fpga, &features); 468 469 if (versions.video_channel) 470 printf("Videochannel"); 471 else 472 printf("Mainchannel"); 473 474 if (versions.con_side) 475 printf(" User"); 476 else 477 printf(" Server"); 478 479// FIXME 480#if 0 481 if (versions & (1<<4)) 482 printf(" UC"); 483#endif 484 485 switch(versions.pcb_transmission_type) { 486 case PCB_CAT_1G: 487 case PCB_CAT_10G: 488 printf(" CAT"); 489 break; 490 case PCB_FIBER_3G: 491 case PCB_FIBER_10G: 492 printf(" Fiber"); 493 break; 494 }; 495 496 switch (versions.pcb_video_type) { 497 case PCB_DVI_SL: 498 printf(" DVI,"); 499 break; 500 case PCB_DP_165MPIX: 501 printf(" DP 165MPix/s,"); 502 break; 503 case PCB_DP_300MPIX: 504 printf(" DP 300MPix/s,"); 505 break; 506 case PCB_HDMI: 507 printf(" HDMI,"); 508 break; 509 case PCB_DP_1_2: 510 printf(" DP 1.2,"); 511 break; 512 case PCB_HDMI_2_0: 513 printf(" HDMI 2.0,"); 514 break; 515 } 516 517 printf(" FPGA V %d.%02d\n features: ", 518 fpga_version / 100, fpga_version % 100); 519 520 if (!features.compression_type1 && 521 !features.compression_type2 && 522 !features.compression_type3) 523 printf("no compression, "); 524 525 if (features.compression_type1) 526 printf("type1, "); 527 528 if (features.compression_type2) 529 printf("type2, "); 530 531 if (features.compression_type3) 532 printf("type3, "); 533 534 printf("%sosd", features.osd ? "" : "no "); 535 536 if (features.pcm_rx && features.pcm_tx) 537 printf(", pcm rx+tx"); 538 else if(features.pcm_rx) 539 printf(", pcm rx"); 540 else if(features.pcm_tx) 541 printf(", pcm tx"); 542 543 if (features.spdif_rx && features.spdif_tx) 544 printf(", spdif rx+tx"); 545 else if(features.spdif_rx) 546 printf(", spdif rx"); 547 else if(features.spdif_tx) 548 printf(", spdif tx"); 549 550 puts(",\n "); 551 552 switch (features.sysclock) { 553 case SYSCLK_147456: 554 printf("clock 147.456 MHz"); 555 break; 556 } 557 558 switch (features.ram_config) { 559 case RAM_DDR2_32BIT_295MBPS: 560 printf(", RAM 32 bit DDR2"); 561 break; 562 case RAM_DDR3_32BIT_590MBPS: 563 printf(", RAM 32 bit DDR3"); 564 break; 565 case RAM_DDR3_48BIT_590MBPS: 566 case RAM_DDR3_48BIT_1800MBPS: 567 printf(", RAM 48 bit DDR3"); 568 break; 569 case RAM_DDR3_64BIT_1800MBPS: 570 printf(", RAM 64 bit DDR3"); 571 break; 572 } 573 574 printf(", %d carrier(s)", features.carriers); 575 576 switch(features.carrier_speed) { 577 case CARRIER_SPEED_1G: 578 printf(", 1Gbit/s"); 579 break; 580 case CARRIER_SPEED_3G: 581 printf(", 3Gbit/s"); 582 break; 583 case CARRIER_SPEED_10G: 584 printf(", 10Gbit/s"); 585 break; 586 } 587 588 printf(", %d video channel(s)\n", features.video_channels); 589} 590 591#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ 592