1#include <common.h>
2#include <command.h>
3#include <console.h> /* ctrlc */
4#include <pci.h>
5#include <asm/io.h>
6
7#include "hydra.h"
8
9enum {
10	HWVER_100 = 0,
11	HWVER_110 = 1,
12	HWVER_120 = 2,
13};
14
15static struct pci_device_id hydra_supported[] = {
16	{ 0x6d5e, 0xcdc1 },
17	{}
18};
19
20static struct ihs_fpga *fpga;
21
22struct ihs_fpga *get_fpga(void)
23{
24	return fpga;
25}
26
27void print_hydra_version(uint index)
28{
29	u32 versions = readl(&fpga->versions);
30	u32 fpga_version = readl(&fpga->fpga_version);
31
32	uint hardware_version = versions & 0xf;
33
34	printf("FPGA%u: mapped to %p\n       ", index, fpga);
35
36	switch (hardware_version) {
37	case HWVER_100:
38		printf("HW-Ver 1.00\n");
39		break;
40
41	case HWVER_110:
42		printf("HW-Ver 1.10\n");
43		break;
44
45	case HWVER_120:
46		printf("HW-Ver 1.20\n");
47		break;
48
49	default:
50		printf("HW-Ver %d(not supported)\n",
51		       hardware_version);
52		break;
53	}
54
55	printf("       FPGA V %d.%02d\n",
56	       fpga_version / 100, fpga_version % 100);
57}
58
59void hydra_initialize(void)
60{
61	uint i;
62	pci_dev_t devno;
63
64	/* Find and probe all the matching PCI devices */
65	for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
66		u32 val;
67
68		/* Try to enable I/O accesses and bus-mastering */
69		val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
70		pci_write_config_dword(devno, PCI_COMMAND, val);
71
72		/* Make sure it worked */
73		pci_read_config_dword(devno, PCI_COMMAND, &val);
74		if (!(val & PCI_COMMAND_MEMORY)) {
75			puts("Can't enable I/O memory\n");
76			continue;
77		}
78		if (!(val & PCI_COMMAND_MASTER)) {
79			puts("Can't enable bus-mastering\n");
80			continue;
81		}
82
83		/* read FPGA details */
84		fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
85				   PCI_REGION_MEM);
86
87		print_hydra_version(i);
88	}
89}
90
91#define REFL_PATTERN (0xdededede)
92#define REFL_PATTERN_INV (~REFL_PATTERN)
93
94int do_hydrate(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
95{
96	uint k = 0;
97	void __iomem *pcie2_base = (void __iomem *)(MVEBU_REG_PCIE_BASE +
98						    0x4000);
99
100	if (!fpga)
101		return -1;
102
103	while (1) {
104		u32 res;
105
106		writel(REFL_PATTERN, &fpga->reflection_low);
107		res = readl(&fpga->reflection_low);
108		if (res != REFL_PATTERN_INV)
109			printf("round %u: read %08x, expected %08x\n",
110			       k, res, REFL_PATTERN_INV);
111		writel(REFL_PATTERN_INV, &fpga->reflection_low);
112		res = readl(&fpga->reflection_low);
113		if (res != REFL_PATTERN)
114			printf("round %u: read %08x, expected %08x\n",
115			       k, res, REFL_PATTERN);
116
117		res = readl(pcie2_base + 0x118) & 0x1f;
118		if (res)
119			printf("FrstErrPtr %u\n", res);
120		res = readl(pcie2_base + 0x104);
121		if (res) {
122			printf("Uncorrectable Error Status 0x%08x\n", res);
123			writel(res, pcie2_base + 0x104);
124		}
125
126		if (!(++k % 10000))
127			printf("round %u\n", k);
128
129		if (ctrlc())
130			break;
131	}
132
133	return 0;
134}
135
136U_BOOT_CMD(
137	hydrate,	1,	0,	do_hydrate,
138	"hydra reflection test",
139	"hydra reflection test"
140);
141