1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 */
5
6#include <common.h>
7#include <i2c.h>
8#include <hwconfig.h>
9#include <init.h>
10#include <log.h>
11#include <asm/global_data.h>
12#include <asm/mmu.h>
13#include <fsl_ddr_sdram.h>
14#include <fsl_ddr_dimm_params.h>
15#include <asm/fsl_law.h>
16#include "ddr.h"
17
18DECLARE_GLOBAL_DATA_PTR;
19
20void fsl_ddr_board_options(memctl_options_t *popts,
21				dimm_params_t *pdimm,
22				unsigned int ctrl_num)
23{
24	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
25	ulong ddr_freq;
26
27	if (ctrl_num > 2) {
28		printf("Not supported controller number %d\n", ctrl_num);
29		return;
30	}
31	if (!pdimm->n_ranks)
32		return;
33
34	/*
35	 * we use identical timing for all slots. If needed, change the code
36	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
37	 */
38	if (popts->registered_dimm_en)
39		pbsp = rdimms[0];
40	else
41		pbsp = udimms[0];
42
43
44	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
45	 * freqency and n_banks specified in board_specific_parameters table.
46	 */
47	ddr_freq = get_ddr_freq(0) / 1000000;
48	while (pbsp->datarate_mhz_high) {
49		if (pbsp->n_ranks == pdimm->n_ranks &&
50		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
51			if (ddr_freq <= pbsp->datarate_mhz_high) {
52				popts->clk_adjust = pbsp->clk_adjust;
53				popts->wrlvl_start = pbsp->wrlvl_start;
54				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
55				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
56				goto found;
57			}
58			pbsp_highest = pbsp;
59		}
60		pbsp++;
61	}
62
63	if (pbsp_highest) {
64		printf("Error: board specific timing not found for data\n"
65			"rate %lu MT/s\n"
66			"Trying to use the highest speed (%u) parameters\n",
67			ddr_freq, pbsp_highest->datarate_mhz_high);
68		popts->clk_adjust = pbsp_highest->clk_adjust;
69		popts->wrlvl_start = pbsp_highest->wrlvl_start;
70		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
71		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
72	} else {
73		panic("DIMM is not supported by this board");
74	}
75found:
76	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
77		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
78		"wrlvl_ctrl_3 0x%x\n",
79		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
80		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
81		pbsp->wrlvl_ctl_3);
82
83	/*
84	 * Factors to consider for half-strength driver enable:
85	 *	- number of DIMMs installed
86	 */
87	popts->half_strength_driver_enable = 0;
88	/*
89	 * Write leveling override
90	 */
91	popts->wrlvl_override = 1;
92	popts->wrlvl_sample = 0xf;
93
94	/*
95	 * Rtt and Rtt_WR override
96	 */
97	popts->rtt_override = 0;
98
99	/* Enable ZQ calibration */
100	popts->zq_en = 1;
101
102	/* DHC_EN =1, ODT = 75 Ohm */
103	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
104	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
105
106	/* optimize cpo for erratum A-009942 */
107	popts->cpo_sample = 0x64;
108}
109
110int dram_init(void)
111{
112	phys_size_t dram_size;
113
114	puts("Initializing....using SPD\n");
115
116#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
117	dram_size = fsl_ddr_sdram();
118#else
119	/* DDR has been initialised by first stage boot loader */
120	dram_size = fsl_ddr_sdram_size();
121#endif
122	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
123	dram_size *= 0x100000;
124
125	gd->ram_size = dram_size;
126
127	return 0;
128}
129