1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2009-2013 Freescale Semiconductor, Inc. 4 * Copyright 2021-2023 NXP 5 */ 6 7#include <common.h> 8#include <command.h> 9#include <env.h> 10#include <fdt_support.h> 11#include <i2c.h> 12#include <image.h> 13#include <init.h> 14#include <netdev.h> 15#include <asm/global_data.h> 16#include <linux/compiler.h> 17#include <asm/mmu.h> 18#include <asm/processor.h> 19#include <asm/immap_85xx.h> 20#include <asm/fsl_law.h> 21#include <asm/fsl_serdes.h> 22#include <asm/fsl_liodn.h> 23#include <clock_legacy.h> 24#include <fm_eth.h> 25#include "t208xrdb.h" 26#include "cpld.h" 27#include "../common/vid.h" 28 29DECLARE_GLOBAL_DATA_PTR; 30 31u8 get_hw_revision(void) 32{ 33 u8 ver = CPLD_READ(hw_ver); 34 35 switch (ver) { 36 default: 37 case 0x1: 38 return 'C'; 39 case 0x0: 40 return 'D'; 41 case 0x2: 42 return 'E'; 43 } 44} 45 46#if CONFIG_IS_ENABLED(DM_SERIAL) 47int get_serial_clock(void) 48{ 49 return get_bus_freq(0) / 2; 50} 51#endif 52 53int checkboard(void) 54{ 55 struct cpu_type *cpu = gd->arch.cpu; 56 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; 57 58 printf("Board: %sRDB, ", cpu->name); 59 printf("Board rev: %c CPLD ver: 0x%02x, boot from ", 60 get_hw_revision(), CPLD_READ(sw_ver)); 61 62#ifdef CONFIG_SDCARD 63 puts("SD/MMC\n"); 64#elif CONFIG_SPIFLASH 65 puts("SPI\n"); 66#else 67 u8 reg; 68 69 reg = CPLD_READ(flash_csr); 70 71 if (reg & CPLD_BOOT_SEL) { 72 puts("NAND\n"); 73 } else { 74 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); 75 printf("NOR vBank%d\n", reg); 76 } 77#endif 78 79 puts("SERDES Reference Clocks:\n"); 80 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); 81 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); 82 83 return 0; 84} 85 86int board_early_init_r(void) 87{ 88 const unsigned int flashbase = CFG_SYS_FLASH_BASE; 89 int flash_esel = find_tlb_idx((void *)flashbase, 1); 90 /* 91 * Remap Boot flash + PROMJET region to caching-inhibited 92 * so that flash can be erased properly. 93 */ 94 95 /* Flush d-cache and invalidate i-cache of any FLASH data */ 96 flush_dcache(); 97 invalidate_icache(); 98 if (flash_esel == -1) { 99 /* very unlikely unless something is messed up */ 100 puts("Error: Could not find TLB for FLASH BASE\n"); 101 flash_esel = 2; /* give our best effort to continue */ 102 } else { 103 /* invalidate existing TLB entry for flash + promjet */ 104 disable_tlb(flash_esel); 105 } 106 107 set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, 108 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 109 0, flash_esel, BOOKE_PAGESZ_256M, 1); 110 111 /* 112 * Adjust core voltage according to voltage ID 113 * This function changes I2C mux to channel 2. 114 */ 115 if (adjust_vdd(0)) 116 printf("Warning: Adjusting core voltage failed.\n"); 117 118 pci_init(); 119 120 return 0; 121} 122 123int misc_init_r(void) 124{ 125 u8 reg; 126 127 /* Reset CS4315 PHY */ 128 reg = CPLD_READ(reset_ctl); 129 reg |= CPLD_RSTCON_EDC_RST; 130 CPLD_WRITE(reset_ctl, reg); 131 132 /* Enable POR for boards revisions D and up */ 133 if (get_hw_revision() >= 'D') { 134 reg = CPLD_READ(misc_csr); 135 reg |= CPLD_MISC_POR_EN; 136 CPLD_WRITE(misc_csr, reg); 137 } 138 139 return 0; 140} 141 142int ft_board_setup(void *blob, struct bd_info *bd) 143{ 144 phys_addr_t base; 145 phys_size_t size; 146 147 ft_cpu_setup(blob, bd); 148 149 base = env_get_bootm_low(); 150 size = env_get_bootm_size(); 151 152 fdt_fixup_memory(blob, (u64)base, (u64)size); 153 154#ifdef CONFIG_PCI 155 pci_of_setup(blob, bd); 156#endif 157 158 fdt_fixup_liodn(blob); 159 fsl_fdt_fixup_dr_usb(blob, bd); 160 161#ifdef CONFIG_SYS_DPAA_FMAN 162 fdt_fixup_board_fman_ethernet(blob); 163 fdt_fixup_board_enet(blob); 164 fdt_fixup_board_phy(blob); 165#endif 166 167 return 0; 168} 169 170ulong *cs4340_get_fw_addr(void) 171{ 172 ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; 173 174#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR 175 u8 reg; 176 177 reg = CPLD_READ(flash_csr); 178 if (!(reg & CPLD_BOOT_SEL)) { 179 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); 180 if (reg == 0) 181 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; 182 else if (reg == 4) 183 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; 184 } 185#endif 186 187 return (ulong *)cortina_fw_addr; 188} 189