1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2009-2013 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7#include <common.h> 8#include <clock_legacy.h> 9#include <command.h> 10#include <env.h> 11#include <fdt_support.h> 12#include <i2c.h> 13#include <image.h> 14#include <init.h> 15#include <log.h> 16#include <netdev.h> 17#include <asm/global_data.h> 18#include <linux/compiler.h> 19#include <asm/mmu.h> 20#include <asm/processor.h> 21#include <asm/immap_85xx.h> 22#include <asm/fsl_law.h> 23#include <asm/fsl_serdes.h> 24#include <asm/fsl_liodn.h> 25#include <fm_eth.h> 26#include "../common/i2c_mux.h" 27 28#include "../common/qixis.h" 29#include "../common/vsc3316_3308.h" 30#include "../common/vid.h" 31#include "t208xqds.h" 32#include "t208xqds_qixis.h" 33 34DECLARE_GLOBAL_DATA_PTR; 35 36int checkboard(void) 37{ 38 char buf[64]; 39 u8 sw; 40 struct cpu_type *cpu = gd->arch.cpu; 41 static const char *freq[4] = { 42 "100.00MHZ(from 8T49N222A)", "125.00MHz", 43 "156.25MHZ", "100.00MHz" 44 }; 45 46 printf("Board: %sQDS, ", cpu->name); 47 sw = QIXIS_READ(arch); 48 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); 49 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); 50 51#ifdef CONFIG_SDCARD 52 puts("SD/MMC\n"); 53#elif CONFIG_SPIFLASH 54 puts("SPI\n"); 55#else 56 sw = QIXIS_READ(brdcfg[0]); 57 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 58 59 if (sw < 0x8) 60 printf("vBank%d\n", sw); 61 else if (sw == 0x8) 62 puts("Promjet\n"); 63 else if (sw == 0x9) 64 puts("NAND\n"); 65 else 66 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 67#endif 68 69 printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), 70 qixis_read_tag(buf), (int)qixis_read_minor()); 71 /* the timestamp string contains "\n" at the end */ 72 printf(" on %s", qixis_read_time(buf)); 73 74 puts("SERDES Reference Clocks:\n"); 75 sw = QIXIS_READ(brdcfg[2]); 76 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], 77 freq[(sw >> 4) & 0x3]); 78 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], 79 freq[sw & 0x3]); 80 81 return 0; 82} 83 84int i2c_multiplexer_select_vid_channel(u8 channel) 85{ 86 return select_i2c_ch_pca9547(channel, 0); 87} 88 89int brd_mux_lane_to_slot(void) 90{ 91 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 92 u32 srds_prtcl_s1; 93 94 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 95 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 96 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 97#if defined(CONFIG_TARGET_T2080QDS) 98 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 99 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 100 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 101#endif 102 103 switch (srds_prtcl_s1) { 104 case 0: 105 /* SerDes1 is not enabled */ 106 break; 107#if defined(CONFIG_TARGET_T2080QDS) 108 case 0x1b: 109 case 0x1c: 110 case 0xa2: 111 /* SD1(A:D) => SLOT3 SGMII 112 * SD1(G:H) => SLOT1 SGMII 113 */ 114 QIXIS_WRITE(brdcfg[12], 0x1a); 115 break; 116 case 0x94: 117 case 0x95: 118 /* SD1(A:B) => SLOT3 SGMII@1.25bps 119 * SD1(C:D) => SFP Module, SGMII@3.125bps 120 * SD1(E:H) => SLOT1 SGMII@1.25bps 121 */ 122 case 0x96: 123 /* SD1(A:B) => SLOT3 SGMII@1.25bps 124 * SD1(C) => SFP Module, SGMII@3.125bps 125 * SD1(D) => SFP Module, SGMII@1.25bps 126 * SD1(E:H) => SLOT1 PCIe4 x4 127 */ 128 QIXIS_WRITE(brdcfg[12], 0x3a); 129 break; 130 case 0x50: 131 case 0x51: 132 /* SD1(A:D) => SLOT3 XAUI 133 * SD1(E) => SLOT1 PCIe4 134 * SD1(F:H) => SLOT2 SGMII 135 */ 136 QIXIS_WRITE(brdcfg[12], 0x15); 137 break; 138 case 0x66: 139 case 0x67: 140 /* SD1(A:D) => 10GBase-R cage 141 * SD1(E:H) => SLOT1 PCIe4 142 */ 143 QIXIS_WRITE(brdcfg[12], 0xfe); 144 break; 145 case 0x6a: 146 case 0x6b: 147 /* SD1(A:D) => 10GBase-R cage 148 * SD1(E) => SLOT1 PCIe4 149 * SD1(F:H) => SLOT2 SGMII 150 */ 151 QIXIS_WRITE(brdcfg[12], 0xf1); 152 break; 153 case 0x6c: 154 case 0x6d: 155 /* SD1(A:B) => 10GBase-R cage 156 * SD1(C:D) => SLOT3 SGMII 157 * SD1(E:H) => SLOT1 PCIe4 158 */ 159 QIXIS_WRITE(brdcfg[12], 0xda); 160 break; 161 case 0x6e: 162 /* SD1(A:B) => SFP Module, 10GBase-R 163 * SD1(C:D) => SLOT3 SGMII 164 * SD1(E:F) => SLOT1 PCIe4 x2 165 * SD1(G:H) => SLOT2 SGMII 166 */ 167 QIXIS_WRITE(brdcfg[12], 0xd9); 168 break; 169 case 0xda: 170 /* SD1(A:H) => SLOT3 PCIe3 x8 171 */ 172 QIXIS_WRITE(brdcfg[12], 0x0); 173 break; 174 case 0xc8: 175 /* SD1(A) => SLOT3 PCIe3 x1 176 * SD1(B) => SFP Module, SGMII@1.25bps 177 * SD1(C:D) => SFP Module, SGMII@3.125bps 178 * SD1(E:F) => SLOT1 PCIe4 x2 179 * SD1(G:H) => SLOT2 SGMII 180 */ 181 QIXIS_WRITE(brdcfg[12], 0x79); 182 break; 183 case 0xab: 184 /* SD1(A:D) => SLOT3 PCIe3 x4 185 * SD1(E:H) => SLOT1 PCIe4 x4 186 */ 187 QIXIS_WRITE(brdcfg[12], 0x1a); 188 break; 189#endif 190 default: 191 printf("WARNING: unsupported for SerDes1 Protocol %d\n", 192 srds_prtcl_s1); 193 return -1; 194 } 195 196#ifdef CONFIG_TARGET_T2080QDS 197 switch (srds_prtcl_s2) { 198 case 0: 199 /* SerDes2 is not enabled */ 200 break; 201 case 0x01: 202 case 0x02: 203 /* SD2(A:H) => SLOT4 PCIe1 */ 204 QIXIS_WRITE(brdcfg[13], 0x10); 205 break; 206 case 0x15: 207 case 0x16: 208 /* 209 * SD2(A:D) => SLOT4 PCIe1 210 * SD2(E:F) => SLOT5 PCIe2 211 * SD2(G:H) => SATA1,SATA2 212 */ 213 QIXIS_WRITE(brdcfg[13], 0xb0); 214 break; 215 case 0x18: 216 /* 217 * SD2(A:D) => SLOT4 PCIe1 218 * SD2(E:F) => SLOT5 Aurora 219 * SD2(G:H) => SATA1,SATA2 220 */ 221 QIXIS_WRITE(brdcfg[13], 0x78); 222 break; 223 case 0x1f: 224 /* 225 * SD2(A:D) => SLOT4 PCIe1 226 * SD2(E:H) => SLOT5 PCIe2 227 */ 228 QIXIS_WRITE(brdcfg[13], 0xa0); 229 break; 230 case 0x29: 231 case 0x2d: 232 case 0x2e: 233 /* 234 * SD2(A:D) => SLOT4 SRIO2 235 * SD2(E:H) => SLOT5 SRIO1 236 */ 237 QIXIS_WRITE(brdcfg[13], 0xa0); 238 break; 239 case 0x36: 240 /* 241 * SD2(A:D) => SLOT4 SRIO2 242 * SD2(E:F) => Aurora 243 * SD2(G:H) => SATA1,SATA2 244 */ 245 QIXIS_WRITE(brdcfg[13], 0x78); 246 break; 247 default: 248 printf("WARNING: unsupported for SerDes2 Protocol %d\n", 249 srds_prtcl_s2); 250 return -1; 251 } 252#endif 253 return 0; 254} 255 256static void esdhc_adapter_card_ident(void) 257{ 258 u8 card_id, value; 259 260 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 261 262 switch (card_id) { 263 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 264 value = QIXIS_READ(brdcfg[5]); 265 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 266 QIXIS_WRITE(brdcfg[5], value); 267 break; 268 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 269 value = QIXIS_READ(pwr_ctl[1]); 270 value |= QIXIS_EVDD_BY_SDHC_VS; 271 QIXIS_WRITE(pwr_ctl[1], value); 272 break; 273 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 274 value = QIXIS_READ(brdcfg[5]); 275 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 276 QIXIS_WRITE(brdcfg[5], value); 277 break; 278 default: 279 break; 280 } 281} 282 283int board_early_init_r(void) 284{ 285 const unsigned int flashbase = CFG_SYS_FLASH_BASE; 286 int flash_esel = find_tlb_idx((void *)flashbase, 1); 287 288 /* 289 * Remap Boot flash + PROMJET region to caching-inhibited 290 * so that flash can be erased properly. 291 */ 292 293 /* Flush d-cache and invalidate i-cache of any FLASH data */ 294 flush_dcache(); 295 invalidate_icache(); 296 297 if (flash_esel == -1) { 298 /* very unlikely unless something is messed up */ 299 puts("Error: Could not find TLB for FLASH BASE\n"); 300 flash_esel = 2; /* give our best effort to continue */ 301 } else { 302 /* invalidate existing TLB entry for flash + promjet */ 303 disable_tlb(flash_esel); 304 } 305 306 set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, 307 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 308 0, flash_esel, BOOKE_PAGESZ_256M, 1); 309 310 /* Disable remote I2C connection to qixis fpga */ 311 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); 312 313 /* 314 * Adjust core voltage according to voltage ID 315 * This function changes I2C mux to channel 2. 316 */ 317 if (adjust_vdd(0)) 318 printf("Warning: Adjusting core voltage failed.\n"); 319 320 brd_mux_lane_to_slot(); 321 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); 322 esdhc_adapter_card_ident(); 323 return 0; 324} 325 326unsigned long get_board_sys_clk(void) 327{ 328 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 329#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT 330 /* use accurate clock measurement */ 331 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); 332 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); 333 u32 val; 334 335 val = freq * base; 336 if (val) { 337 debug("SYS Clock measurement is: %d\n", val); 338 return val; 339 } else { 340 printf("Warning: SYS clock measurement is invalid, "); 341 printf("using value from brdcfg1.\n"); 342 } 343#endif 344 345 switch (sysclk_conf & 0x0F) { 346 case QIXIS_SYSCLK_83: 347 return 83333333; 348 case QIXIS_SYSCLK_100: 349 return 100000000; 350 case QIXIS_SYSCLK_125: 351 return 125000000; 352 case QIXIS_SYSCLK_133: 353 return 133333333; 354 case QIXIS_SYSCLK_150: 355 return 150000000; 356 case QIXIS_SYSCLK_160: 357 return 160000000; 358 case QIXIS_SYSCLK_166: 359 return 166666666; 360 } 361 return 66666666; 362} 363 364unsigned long get_board_ddr_clk(void) 365{ 366 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 367#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT 368 /* use accurate clock measurement */ 369 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); 370 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); 371 u32 val; 372 373 val = freq * base; 374 if (val) { 375 debug("DDR Clock measurement is: %d\n", val); 376 return val; 377 } else { 378 printf("Warning: DDR clock measurement is invalid, "); 379 printf("using value from brdcfg1.\n"); 380 } 381#endif 382 383 switch ((ddrclk_conf & 0x30) >> 4) { 384 case QIXIS_DDRCLK_100: 385 return 100000000; 386 case QIXIS_DDRCLK_125: 387 return 125000000; 388 case QIXIS_DDRCLK_133: 389 return 133333333; 390 } 391 return 66666666; 392} 393 394int misc_init_r(void) 395{ 396 return 0; 397} 398 399int ft_board_setup(void *blob, struct bd_info *bd) 400{ 401 phys_addr_t base; 402 phys_size_t size; 403 404 ft_cpu_setup(blob, bd); 405 406 base = env_get_bootm_low(); 407 size = env_get_bootm_size(); 408 409 fdt_fixup_memory(blob, (u64)base, (u64)size); 410 411#ifdef CONFIG_PCI 412 pci_of_setup(blob, bd); 413#endif 414 415 fdt_fixup_liodn(blob); 416 fsl_fdt_fixup_dr_usb(blob, bd); 417 418#ifdef CONFIG_SYS_DPAA_FMAN 419#ifndef CONFIG_DM_ETH 420 fdt_fixup_fman_ethernet(blob); 421#endif 422 fdt_fixup_board_enet(blob); 423#endif 424 425 return 0; 426} 427