1// SPDX-License-Identifier: GPL-2.0+ 2/* Copyright 2013 Freescale Semiconductor, Inc. 3 */ 4 5#include <common.h> 6#include <clock_legacy.h> 7#include <console.h> 8#include <env_internal.h> 9#include <init.h> 10#include <malloc.h> 11#include <ns16550.h> 12#include <nand.h> 13#include <i2c.h> 14#include <mmc.h> 15#include <fsl_esdhc.h> 16#include <spi_flash.h> 17#include <asm/global_data.h> 18#include "../common/qixis.h" 19#include "t208xqds_qixis.h" 20#include "../common/spl.h" 21 22DECLARE_GLOBAL_DATA_PTR; 23 24phys_size_t get_effective_memsize(void) 25{ 26 return CONFIG_SYS_L3_SIZE; 27} 28 29unsigned long get_board_sys_clk(void) 30{ 31 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 32 33 switch (sysclk_conf & 0x0F) { 34 case QIXIS_SYSCLK_83: 35 return 83333333; 36 case QIXIS_SYSCLK_100: 37 return 100000000; 38 case QIXIS_SYSCLK_125: 39 return 125000000; 40 case QIXIS_SYSCLK_133: 41 return 133333333; 42 case QIXIS_SYSCLK_150: 43 return 150000000; 44 case QIXIS_SYSCLK_160: 45 return 160000000; 46 case QIXIS_SYSCLK_166: 47 return 166666666; 48 } 49 return 66666666; 50} 51 52unsigned long get_board_ddr_clk(void) 53{ 54 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 55 56 switch ((ddrclk_conf & 0x30) >> 4) { 57 case QIXIS_DDRCLK_100: 58 return 100000000; 59 case QIXIS_DDRCLK_125: 60 return 125000000; 61 case QIXIS_DDRCLK_133: 62 return 133333333; 63 } 64 return 66666666; 65} 66 67void board_init_f(ulong bootflag) 68{ 69 u32 plat_ratio, sys_clk, ccb_clk; 70 ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; 71 72 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 73 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 74 75 /* Update GD pointer */ 76 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 77 78 console_init_f(); 79 80 /* initialize selected port with appropriate baud rate */ 81 sys_clk = get_board_sys_clk(); 82 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 83 ccb_clk = sys_clk * plat_ratio / 2; 84 85 ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, 86 ccb_clk / 16 / CONFIG_BAUDRATE); 87 88#if defined(CONFIG_SPL_MMC_BOOT) 89 puts("\nSD boot...\n"); 90#elif defined(CONFIG_SPL_SPI_BOOT) 91 puts("\nSPI boot...\n"); 92#elif defined(CONFIG_SPL_NAND_BOOT) 93 puts("\nNAND boot...\n"); 94#endif 95 96 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 97} 98 99void board_init_r(gd_t *gd, ulong dest_addr) 100{ 101 struct bd_info *bd; 102 103 bd = (struct bd_info *)(gd + sizeof(gd_t)); 104 memset(bd, 0, sizeof(struct bd_info)); 105 gd->bd = bd; 106 107 arch_cpu_init(); 108 get_clocks(); 109 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 110 CONFIG_SPL_RELOC_MALLOC_SIZE); 111 gd->flags |= GD_FLG_FULL_MALLOC_INIT; 112 113#ifdef CONFIG_SPL_NAND_BOOT 114 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 115 (uchar *)SPL_ENV_ADDR); 116#endif 117#ifdef CONFIG_SPL_MMC_BOOT 118 mmc_initialize(bd); 119 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 120 (uchar *)SPL_ENV_ADDR); 121#endif 122#ifdef CONFIG_SPL_SPI_BOOT 123 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 124 (uchar *)SPL_ENV_ADDR); 125#endif 126 127 gd->env_addr = (ulong)(SPL_ENV_ADDR); 128 gd->env_valid = ENV_VALID; 129 130 i2c_init_all(); 131 132 dram_init(); 133 134#ifdef CONFIG_SPL_MMC_BOOT 135 mmc_boot(); 136#elif defined(CONFIG_SPL_SPI_BOOT) 137 fsl_spi_boot(); 138#elif defined(CONFIG_SPL_NAND_BOOT) 139 nand_boot(); 140#endif 141} 142