1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 * 6 * Shengzhou Liu <Shengzhou.Liu@freescale.com> 7 */ 8 9#include <common.h> 10#include <command.h> 11#include <fdt_support.h> 12#include <log.h> 13#include <net.h> 14#include <netdev.h> 15#include <asm/mmu.h> 16#include <asm/processor.h> 17#include <asm/immap_85xx.h> 18#include <asm/fsl_law.h> 19#include <asm/fsl_serdes.h> 20#include <asm/fsl_portals.h> 21#include <asm/fsl_liodn.h> 22#include <malloc.h> 23#include <fm_eth.h> 24#include <fsl_mdio.h> 25#include <miiphy.h> 26#include <phy.h> 27#include <fsl_dtsec.h> 28#include <asm/fsl_serdes.h> 29#include <hwconfig.h> 30#include "../common/qixis.h" 31#include "../common/fman.h" 32#include "t208xqds_qixis.h" 33#include <linux/libfdt.h> 34 35#define EMI_NONE 0xFFFFFFFF 36#define EMI1_RGMII1 0 37#define EMI1_RGMII2 1 38#define EMI1_SLOT1 2 39#if defined(CONFIG_TARGET_T2080QDS) 40#define EMI1_SLOT2 6 41#define EMI1_SLOT3 3 42#define EMI1_SLOT4 4 43#define EMI1_SLOT5 5 44#define EMI2 7 45#endif 46 47#define PCCR1_SGMIIA_KX_MASK 0x00008000 48#define PCCR1_SGMIIB_KX_MASK 0x00004000 49#define PCCR1_SGMIIC_KX_MASK 0x00002000 50#define PCCR1_SGMIID_KX_MASK 0x00001000 51#define PCCR1_SGMIIE_KX_MASK 0x00000800 52#define PCCR1_SGMIIF_KX_MASK 0x00000400 53#define PCCR1_SGMIIG_KX_MASK 0x00000200 54#define PCCR1_SGMIIH_KX_MASK 0x00000100 55 56static int mdio_mux[NUM_FM_PORTS]; 57 58static const char * const mdio_names[] = { 59#if defined(CONFIG_TARGET_T2080QDS) 60 "T2080QDS_MDIO_RGMII1", 61 "T2080QDS_MDIO_RGMII2", 62 "T2080QDS_MDIO_SLOT1", 63 "T2080QDS_MDIO_SLOT3", 64 "T2080QDS_MDIO_SLOT4", 65 "T2080QDS_MDIO_SLOT5", 66 "T2080QDS_MDIO_SLOT2", 67 "T2080QDS_MDIO_10GC", 68#endif 69}; 70 71/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ 72#if defined(CONFIG_TARGET_T2080QDS) 73static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; 74#endif 75 76static const char *t208xqds_mdio_name_for_muxval(u8 muxval) 77{ 78 return mdio_names[muxval]; 79} 80 81struct mii_dev *mii_dev_for_muxval(u8 muxval) 82{ 83 struct mii_dev *bus; 84 const char *name = t208xqds_mdio_name_for_muxval(muxval); 85 86 if (!name) { 87 printf("No bus for muxval %x\n", muxval); 88 return NULL; 89 } 90 91 bus = miiphy_get_dev_by_name(name); 92 93 if (!bus) { 94 printf("No bus by name %s\n", name); 95 return NULL; 96 } 97 98 return bus; 99} 100 101struct t208xqds_mdio { 102 u8 muxval; 103 struct mii_dev *realbus; 104}; 105 106static void t208xqds_mux_mdio(u8 muxval) 107{ 108 u8 brdcfg4; 109 if (muxval < 8) { 110 brdcfg4 = QIXIS_READ(brdcfg[4]); 111 brdcfg4 &= ~BRDCFG4_EMISEL_MASK; 112 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); 113 QIXIS_WRITE(brdcfg[4], brdcfg4); 114 } 115} 116 117static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, 118 int regnum) 119{ 120 struct t208xqds_mdio *priv = bus->priv; 121 122 t208xqds_mux_mdio(priv->muxval); 123 124 return priv->realbus->read(priv->realbus, addr, devad, regnum); 125} 126 127static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, 128 int regnum, u16 value) 129{ 130 struct t208xqds_mdio *priv = bus->priv; 131 132 t208xqds_mux_mdio(priv->muxval); 133 134 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 135} 136 137static int t208xqds_mdio_reset(struct mii_dev *bus) 138{ 139 struct t208xqds_mdio *priv = bus->priv; 140 141 return priv->realbus->reset(priv->realbus); 142} 143 144static int t208xqds_mdio_init(char *realbusname, u8 muxval) 145{ 146 struct t208xqds_mdio *pmdio; 147 struct mii_dev *bus = mdio_alloc(); 148 149 if (!bus) { 150 printf("Failed to allocate t208xqds MDIO bus\n"); 151 return -1; 152 } 153 154 pmdio = malloc(sizeof(*pmdio)); 155 if (!pmdio) { 156 printf("Failed to allocate t208xqds private data\n"); 157 free(bus); 158 return -1; 159 } 160 161 bus->read = t208xqds_mdio_read; 162 bus->write = t208xqds_mdio_write; 163 bus->reset = t208xqds_mdio_reset; 164 strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); 165 166 pmdio->realbus = miiphy_get_dev_by_name(realbusname); 167 168 if (!pmdio->realbus) { 169 printf("No bus with name %s\n", realbusname); 170 free(bus); 171 free(pmdio); 172 return -1; 173 } 174 175 pmdio->muxval = muxval; 176 bus->priv = pmdio; 177 return mdio_register(bus); 178} 179 180void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 181 enum fm_port port, int offset) 182{ 183 int phy; 184 char alias[20]; 185 char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; 186 char buf[32] = "serdes-1,"; 187 struct fixed_link f_link; 188 int media_type = 0; 189 const char *phyconn; 190 int off; 191 192 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 193#ifdef CONFIG_TARGET_T2080QDS 194 serdes_corenet_t *srds_regs = 195 (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; 196 u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); 197#endif 198 u32 srds_s1 = in_be32(&gur->rcwsr[4]) & 199 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 200 201 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 202 203 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { 204 phy = fm_info_get_phy_address(port); 205 switch (port) { 206#if defined(CONFIG_TARGET_T2080QDS) 207 case FM1_DTSEC1: 208 if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { 209 media_type = 1; 210 fdt_set_phy_handle(fdt, compat, addr, 211 "phy_1gkx1"); 212 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); 213 sprintf(buf, "%s%s%s", buf, "lane-c,", 214 (char *)lane_mode[0]); 215 out_be32(&srds_regs->srdspccr1, srds1_pccr1 | 216 PCCR1_SGMIIH_KX_MASK); 217 break; 218 } 219 case FM1_DTSEC2: 220 if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { 221 media_type = 1; 222 fdt_set_phy_handle(fdt, compat, addr, 223 "phy_1gkx2"); 224 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); 225 sprintf(buf, "%s%s%s", buf, "lane-d,", 226 (char *)lane_mode[0]); 227 out_be32(&srds_regs->srdspccr1, srds1_pccr1 | 228 PCCR1_SGMIIG_KX_MASK); 229 break; 230 } 231 case FM1_DTSEC9: 232 if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { 233 media_type = 1; 234 fdt_set_phy_handle(fdt, compat, addr, 235 "phy_1gkx9"); 236 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); 237 sprintf(buf, "%s%s%s", buf, "lane-a,", 238 (char *)lane_mode[0]); 239 out_be32(&srds_regs->srdspccr1, srds1_pccr1 | 240 PCCR1_SGMIIE_KX_MASK); 241 break; 242 } 243 case FM1_DTSEC10: 244 if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { 245 media_type = 1; 246 fdt_set_phy_handle(fdt, compat, addr, 247 "phy_1gkx10"); 248 fdt_status_okay_by_alias(fdt, 249 "1gkx_pcs_mdio10"); 250 sprintf(buf, "%s%s%s", buf, "lane-b,", 251 (char *)lane_mode[0]); 252 out_be32(&srds_regs->srdspccr1, srds1_pccr1 | 253 PCCR1_SGMIIF_KX_MASK); 254 break; 255 } 256 if (mdio_mux[port] == EMI1_SLOT2) { 257 sprintf(alias, "phy_sgmii_s2_%x", phy); 258 fdt_set_phy_handle(fdt, compat, addr, alias); 259 fdt_status_okay_by_alias(fdt, "emi1_slot2"); 260 } else if (mdio_mux[port] == EMI1_SLOT3) { 261 sprintf(alias, "phy_sgmii_s3_%x", phy); 262 fdt_set_phy_handle(fdt, compat, addr, alias); 263 fdt_status_okay_by_alias(fdt, "emi1_slot3"); 264 } 265 break; 266 case FM1_DTSEC5: 267 if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { 268 media_type = 1; 269 fdt_set_phy_handle(fdt, compat, addr, 270 "phy_1gkx5"); 271 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); 272 sprintf(buf, "%s%s%s", buf, "lane-g,", 273 (char *)lane_mode[0]); 274 out_be32(&srds_regs->srdspccr1, srds1_pccr1 | 275 PCCR1_SGMIIC_KX_MASK); 276 break; 277 } 278 case FM1_DTSEC6: 279 if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { 280 media_type = 1; 281 fdt_set_phy_handle(fdt, compat, addr, 282 "phy_1gkx6"); 283 fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); 284 sprintf(buf, "%s%s%s", buf, "lane-h,", 285 (char *)lane_mode[0]); 286 out_be32(&srds_regs->srdspccr1, srds1_pccr1 | 287 PCCR1_SGMIID_KX_MASK); 288 break; 289 } 290 if (mdio_mux[port] == EMI1_SLOT1) { 291 sprintf(alias, "phy_sgmii_s1_%x", phy); 292 fdt_set_phy_handle(fdt, compat, addr, alias); 293 fdt_status_okay_by_alias(fdt, "emi1_slot1"); 294 } else if (mdio_mux[port] == EMI1_SLOT2) { 295 sprintf(alias, "phy_sgmii_s2_%x", phy); 296 fdt_set_phy_handle(fdt, compat, addr, alias); 297 fdt_status_okay_by_alias(fdt, "emi1_slot2"); 298 } 299 break; 300#endif 301 default: 302 break; 303 } 304 if (media_type) { 305 /* set property for 1000BASE-KX in dtb */ 306 off = fdt_node_offset_by_compat_reg(fdt, 307 "fsl,fman-memac-mdio", addr + 0x1000); 308 fdt_setprop_string(fdt, off, "lane-instance", buf); 309 } 310 311 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { 312 switch (srds_s1) { 313 case 0x66: /* 10GBase-R interface */ 314 case 0x6b: 315 case 0x6c: 316 case 0x6d: 317 case 0x71: 318 /* 319 * Check hwconfig to see what is the media type, there 320 * are two types, fiber or copper, fix the dtb 321 * accordingly. 322 */ 323 switch (port) { 324 case FM1_10GEC1: 325 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { 326 /* it's MAC9 */ 327 media_type = 1; 328 fdt_set_phy_handle(fdt, compat, addr, 329 "phy_xfi9"); 330 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); 331 sprintf(buf, "%s%s%s", buf, "lane-a,", 332 (char *)lane_mode[1]); 333 } 334 break; 335 case FM1_10GEC2: 336 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { 337 /* it's MAC10 */ 338 media_type = 1; 339 fdt_set_phy_handle(fdt, compat, addr, 340 "phy_xfi10"); 341 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); 342 sprintf(buf, "%s%s%s", buf, "lane-b,", 343 (char *)lane_mode[1]); 344 } 345 break; 346 case FM1_10GEC3: 347 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { 348 /* it's MAC1 */ 349 media_type = 1; 350 fdt_set_phy_handle(fdt, compat, addr, 351 "phy_xfi1"); 352 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); 353 sprintf(buf, "%s%s%s", buf, "lane-c,", 354 (char *)lane_mode[1]); 355 } 356 break; 357 case FM1_10GEC4: 358 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { 359 /* it's MAC2 */ 360 media_type = 1; 361 fdt_set_phy_handle(fdt, compat, addr, 362 "phy_xfi2"); 363 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); 364 sprintf(buf, "%s%s%s", buf, "lane-d,", 365 (char *)lane_mode[1]); 366 } 367 break; 368 default: 369 return; 370 } 371 372 if (!media_type) { 373 phyconn = fdt_getprop(fdt, offset, 374 "phy-connection-type", 375 NULL); 376 if (is_backplane_mode(phyconn)) { 377 /* Backplane KR mode: skip fixups */ 378 printf("Interface %d in backplane KR mode\n", 379 port); 380 } else { 381 /* fixed-link for 10GBase-R fiber cable */ 382 f_link.phy_id = port; 383 f_link.duplex = 1; 384 f_link.link_speed = 10000; 385 f_link.pause = 0; 386 f_link.asym_pause = 0; 387 fdt_delprop(fdt, offset, "phy-handle"); 388 fdt_setprop(fdt, offset, "fixed-link", 389 &f_link, sizeof(f_link)); 390 } 391 } else { 392 /* set property for copper cable */ 393 off = fdt_node_offset_by_compat_reg(fdt, 394 "fsl,fman-memac-mdio", addr + 0x1000); 395 fdt_setprop_string(fdt, off, 396 "lane-instance", buf); 397 } 398 break; 399 default: 400 break; 401 } 402 } 403} 404 405void fdt_fixup_board_enet(void *fdt) 406{ 407 return; 408} 409 410/* 411 * This function reads RCW to check if Serdes1{A:H} is configured 412 * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly 413 */ 414static void initialize_lane_to_slot(void) 415{ 416 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 417 u32 srds_s1 = in_be32(&gur->rcwsr[4]) & 418 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 419 420 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 421 422 switch (srds_s1) { 423#if defined(CONFIG_TARGET_T2080QDS) 424 case 0x51: 425 case 0x5f: 426 case 0x65: 427 case 0x6b: 428 case 0x71: 429 lane_to_slot[5] = 2; 430 lane_to_slot[6] = 2; 431 lane_to_slot[7] = 2; 432 break; 433 case 0xa6: 434 case 0x8e: 435 case 0x8f: 436 case 0x82: 437 case 0x83: 438 case 0xd3: 439 case 0xd9: 440 case 0xcb: 441 lane_to_slot[6] = 2; 442 lane_to_slot[7] = 2; 443 break; 444 case 0xda: 445 lane_to_slot[4] = 3; 446 lane_to_slot[5] = 3; 447 lane_to_slot[6] = 3; 448 lane_to_slot[7] = 3; 449 break; 450#endif 451 default: 452 break; 453 } 454} 455 456int board_eth_init(struct bd_info *bis) 457{ 458#if defined(CONFIG_FMAN_ENET) 459 int i, idx, lane, slot, interface; 460 struct memac_mdio_info dtsec_mdio_info; 461 struct memac_mdio_info tgec_mdio_info; 462 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 463 u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 464 u32 srds_s1; 465 466 srds_s1 = in_be32(&gur->rcwsr[4]) & 467 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 468 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 469 470 initialize_lane_to_slot(); 471 472 /* Initialize the mdio_mux array so we can recognize empty elements */ 473 for (i = 0; i < NUM_FM_PORTS; i++) 474 mdio_mux[i] = EMI_NONE; 475 476 dtsec_mdio_info.regs = 477 (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; 478 479 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 480 481 /* Register the 1G MDIO bus */ 482 fm_memac_mdio_init(bis, &dtsec_mdio_info); 483 484 tgec_mdio_info.regs = 485 (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; 486 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 487 488 /* Register the 10G MDIO bus */ 489 fm_memac_mdio_init(bis, &tgec_mdio_info); 490 491 /* Register the muxing front-ends to the MDIO buses */ 492 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); 493 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); 494 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); 495 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); 496 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); 497#if defined(CONFIG_TARGET_T2080QDS) 498 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); 499#endif 500 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); 501 t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); 502 503 /* Set the two on-board RGMII PHY address */ 504 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); 505 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 506 FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) 507 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); 508 else 509 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); 510 511 switch (srds_s1) { 512 case 0x1b: 513 case 0x1c: 514 case 0x95: 515 case 0xa2: 516 case 0x94: 517 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ 518 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); 519 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); 520 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 521 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 522 /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ 523 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 524 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); 525 break; 526 case 0x50: 527 case 0x51: 528 case 0x5e: 529 case 0x5f: 530 case 0x64: 531 case 0x65: 532 /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ 533 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); 534 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ 535 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 536 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); 537 break; 538 case 0x66: 539 case 0x67: 540 /* 541 * 10GBase-R does not need a PHY to work, but to avoid U-Boot 542 * use default PHY address which is zero to a MAC when it found 543 * a MAC has no PHY address, we give a PHY address to 10GBase-R 544 * MAC, and should not use a real XAUI PHY address, since 545 * MDIO can access it successfully, and then MDIO thinks 546 * the XAUI card is used for the 10GBase-R MAC, which will cause 547 * error. 548 */ 549 fm_info_set_phy_address(FM1_10GEC1, 4); 550 fm_info_set_phy_address(FM1_10GEC2, 5); 551 fm_info_set_phy_address(FM1_10GEC3, 6); 552 fm_info_set_phy_address(FM1_10GEC4, 7); 553 break; 554 case 0x6a: 555 case 0x6b: 556 fm_info_set_phy_address(FM1_10GEC1, 4); 557 fm_info_set_phy_address(FM1_10GEC2, 5); 558 fm_info_set_phy_address(FM1_10GEC3, 6); 559 fm_info_set_phy_address(FM1_10GEC4, 7); 560 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ 561 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 562 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 563 break; 564 case 0x6c: 565 case 0x6d: 566 fm_info_set_phy_address(FM1_10GEC1, 4); 567 fm_info_set_phy_address(FM1_10GEC2, 5); 568 /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ 569 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 570 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 571 break; 572 case 0x70: 573 case 0x71: 574 /* SGMII in Slot3 */ 575 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 576 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 577 /* SGMII in Slot2 */ 578 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 579 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 580 break; 581 case 0xa6: 582 case 0x8e: 583 case 0x8f: 584 case 0x82: 585 case 0x83: 586 /* SGMII in Slot3 */ 587 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); 588 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); 589 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 590 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 591 /* SGMII in Slot2 */ 592 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 593 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 594 break; 595 case 0xa4: 596 case 0x96: 597 case 0x8a: 598 /* SGMII in Slot3 */ 599 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); 600 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); 601 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 602 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 603 break; 604#if defined(CONFIG_TARGET_T2080QDS) 605 case 0xd9: 606 case 0xd3: 607 case 0xcb: 608 /* SGMII in Slot3 */ 609 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); 610 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 611 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 612 /* SGMII in Slot2 */ 613 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 614 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 615 break; 616#endif 617 case 0xf2: 618 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ 619 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); 620 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); 621 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); 622 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); 623 break; 624 default: 625 break; 626 } 627 628 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { 629 idx = i - FM1_DTSEC1; 630 interface = fm_info_get_enet_if(i); 631 switch (interface) { 632 case PHY_INTERFACE_MODE_SGMII: 633 lane = serdes_get_first_lane(FSL_SRDS_1, 634 SGMII_FM1_DTSEC1 + idx); 635 if (lane < 0) 636 break; 637 slot = lane_to_slot[lane]; 638 debug("FM1@DTSEC%u expects SGMII in slot %u\n", 639 idx + 1, slot); 640 if (QIXIS_READ(present2) & (1 << (slot - 1))) 641 fm_disable_port(i); 642 643 switch (slot) { 644 case 1: 645 mdio_mux[i] = EMI1_SLOT1; 646 fm_info_set_mdio(i, mii_dev_for_muxval( 647 mdio_mux[i])); 648 break; 649 case 2: 650 mdio_mux[i] = EMI1_SLOT2; 651 fm_info_set_mdio(i, mii_dev_for_muxval( 652 mdio_mux[i])); 653 break; 654 case 3: 655 mdio_mux[i] = EMI1_SLOT3; 656 fm_info_set_mdio(i, mii_dev_for_muxval( 657 mdio_mux[i])); 658 break; 659 } 660 break; 661 case PHY_INTERFACE_MODE_RGMII: 662 case PHY_INTERFACE_MODE_RGMII_TXID: 663 case PHY_INTERFACE_MODE_RGMII_RXID: 664 case PHY_INTERFACE_MODE_RGMII_ID: 665 if (i == FM1_DTSEC3) 666 mdio_mux[i] = EMI1_RGMII1; 667 else if (i == FM1_DTSEC4 || FM1_DTSEC10) 668 mdio_mux[i] = EMI1_RGMII2; 669 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 670 break; 671 default: 672 break; 673 } 674 } 675 676 for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { 677 idx = i - FM1_10GEC1; 678 switch (fm_info_get_enet_if(i)) { 679 case PHY_INTERFACE_MODE_XGMII: 680 if (srds_s1 == 0x51) { 681 lane = serdes_get_first_lane(FSL_SRDS_1, 682 XAUI_FM1_MAC9 + idx); 683 } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { 684 lane = serdes_get_first_lane(FSL_SRDS_1, 685 HIGIG_FM1_MAC9 + idx); 686 } else { 687 if (i == FM1_10GEC1 || i == FM1_10GEC2) 688 lane = serdes_get_first_lane(FSL_SRDS_1, 689 XFI_FM1_MAC9 + idx); 690 else 691 lane = serdes_get_first_lane(FSL_SRDS_1, 692 XFI_FM1_MAC1 + idx); 693 } 694 695 if (lane < 0) 696 break; 697 mdio_mux[i] = EMI2; 698 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 699 700 if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || 701 (srds_s1 == 0x6a) || (srds_s1 == 0x70) || 702 (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || 703 (srds_s1 == 0x71)) { 704 /* As 10GBase-R is in cage intead of a slot, so 705 * ensure doesn't disable the corresponding port 706 */ 707 break; 708 } 709 710 slot = lane_to_slot[lane]; 711 if (QIXIS_READ(present2) & (1 << (slot - 1))) 712 fm_disable_port(i); 713 break; 714 default: 715 break; 716 } 717 } 718 719 cpu_eth_init(bis); 720#endif /* CONFIG_FMAN_ENET */ 721 722 return pci_eth_init(bis); 723} 724