1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * Copyright 2021 NXP 5 */ 6 7#include <common.h> 8#include <i2c.h> 9#include <hwconfig.h> 10#include <init.h> 11#include <log.h> 12#include <asm/global_data.h> 13#include <asm/mmu.h> 14#include <fsl_ddr_sdram.h> 15#include <fsl_ddr_dimm_params.h> 16#include <asm/fsl_law.h> 17#include <asm/mpc85xx_gpio.h> 18#include <linux/delay.h> 19#include "ddr.h" 20 21DECLARE_GLOBAL_DATA_PTR; 22 23void fsl_ddr_board_options(memctl_options_t *popts, 24 dimm_params_t *pdimm, 25 unsigned int ctrl_num) 26{ 27 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 28 ulong ddr_freq; 29 30 if (ctrl_num > 1) { 31 printf("Not supported controller number %d\n", ctrl_num); 32 return; 33 } 34 if (!pdimm->n_ranks) 35 return; 36 37 pbsp = udimms[0]; 38 39 /* Get clk_adjust according to the board ddr 40 * freqency and n_banks specified in board_specific_parameters table. 41 */ 42 ddr_freq = get_ddr_freq(0) / 1000000; 43 while (pbsp->datarate_mhz_high) { 44 if (pbsp->n_ranks == pdimm->n_ranks && 45 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 46 if (ddr_freq <= pbsp->datarate_mhz_high) { 47 popts->clk_adjust = pbsp->clk_adjust; 48 popts->wrlvl_start = pbsp->wrlvl_start; 49 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 50 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 51 goto found; 52 } 53 pbsp_highest = pbsp; 54 } 55 pbsp++; 56 } 57 58 if (pbsp_highest) { 59 printf("Error: board specific timing not found\n"); 60 printf("for data rate %lu MT/s\n", ddr_freq); 61 printf("Trying to use the highest speed (%u) parameters\n", 62 pbsp_highest->datarate_mhz_high); 63 popts->clk_adjust = pbsp_highest->clk_adjust; 64 popts->wrlvl_start = pbsp_highest->wrlvl_start; 65 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 66 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 67 } else { 68 panic("DIMM is not supported by this board"); 69 } 70found: 71 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 72 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " 73 "wrlvl_ctrl_3 0x%x\n", 74 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 75 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 76 pbsp->wrlvl_ctl_3); 77 78 /* 79 * Factors to consider for half-strength driver enable: 80 * - number of DIMMs installed 81 */ 82#ifdef CONFIG_SYS_FSL_DDR4 83 popts->half_strength_driver_enable = 1; 84 /* optimize cpo for erratum A-009942 */ 85 popts->cpo_sample = 0x59; 86#else 87 popts->cpo_sample = 0x54; 88 popts->half_strength_driver_enable = 0; 89#endif 90 /* 91 * Write leveling override 92 */ 93 popts->wrlvl_override = 1; 94 popts->wrlvl_sample = 0xf; 95 96 /* 97 * rtt and rtt_wr override 98 */ 99 popts->rtt_override = 0; 100 101 /* Enable ZQ calibration */ 102 popts->zq_en = 1; 103 104 /* DHC_EN =1, ODT = 75 Ohm */ 105#ifdef CONFIG_SYS_FSL_DDR4 106 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM); 107 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) | 108 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 109#else 110 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 111 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 112#endif 113} 114 115#if defined(CONFIG_DEEP_SLEEP) 116void board_mem_sleep_setup(void) 117{ 118 void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE; 119 120 /* does not provide HW signals for power management */ 121 clrbits_8(cpld_base + 0x17, 0x40); 122 /* Disable MCKE isolation */ 123 gpio_set_value(2, 0); 124 udelay(1); 125} 126#endif 127 128int dram_init(void) 129{ 130 phys_size_t dram_size; 131 132#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 133 puts("Initializing....using SPD\n"); 134 dram_size = fsl_ddr_sdram(); 135#else 136 dram_size = fsl_ddr_sdram_size(); 137#endif 138 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 139 dram_size *= 0x100000; 140 141#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 142 fsl_dp_resume(); 143#endif 144 145 gd->ram_size = dram_size; 146 147 return 0; 148} 149