1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2023 NXP
5 */
6
7#include <common.h>
8#include <command.h>
9#include <env.h>
10#include <fdt_support.h>
11#include <i2c.h>
12#include <image.h>
13#include <init.h>
14#include <netdev.h>
15#include <asm/global_data.h>
16#include <linux/compiler.h>
17#include <asm/mmu.h>
18#include <asm/processor.h>
19#include <asm/immap_85xx.h>
20#include <asm/fsl_law.h>
21#include <asm/fsl_serdes.h>
22#include <asm/fsl_liodn.h>
23#include <clock_legacy.h>
24#include <fm_eth.h>
25#include "t102xrdb.h"
26#ifdef CONFIG_TARGET_T1024RDB
27#include "cpld.h"
28#elif defined(CONFIG_TARGET_T1023RDB)
29#include <i2c.h>
30#include <mmc.h>
31#endif
32#include "../common/sleep.h"
33
34DECLARE_GLOBAL_DATA_PTR;
35
36#ifdef CONFIG_TARGET_T1023RDB
37enum {
38	GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
39	GPIO1_EMMC_SEL,
40	GPIO3_GET_VERSION,	       /* GPIO3_4/5, 00:RevB, 01: RevC */
41	GPIO3_BRD_VER_MASK = 0x0c000000,
42	GPIO3_OFFSET = 0x2000,
43	I2C_GET_BANK,
44	I2C_SET_BANK0,
45	I2C_SET_BANK4,
46};
47#endif
48
49#if CONFIG_IS_ENABLED(DM_SERIAL)
50int get_serial_clock(void)
51{
52	return get_bus_freq(0) / 2;
53}
54#endif
55
56int checkboard(void)
57{
58	struct cpu_type *cpu = gd->arch.cpu;
59	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
60	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
61	u32 srds_s1;
62
63	srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
64	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
65
66	printf("Board: %sRDB, ", cpu->name);
67#if defined(CONFIG_TARGET_T1024RDB)
68	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
69	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
70#elif defined(CONFIG_TARGET_T1023RDB)
71	printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
72#endif
73	printf("boot from ");
74
75#ifdef CONFIG_SDCARD
76	puts("SD/MMC\n");
77#elif CONFIG_SPIFLASH
78	puts("SPI\n");
79#elif defined(CONFIG_TARGET_T1024RDB)
80	u8 reg;
81
82	reg = CPLD_READ(flash_csr);
83
84	if (reg & CPLD_BOOT_SEL) {
85		puts("NAND\n");
86	} else {
87		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
88		printf("NOR vBank%d\n", reg);
89	}
90#elif defined(CONFIG_TARGET_T1023RDB)
91#ifdef CONFIG_MTD_RAW_NAND
92	puts("NAND\n");
93#else
94	printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
95#endif
96#endif
97
98	puts("SERDES Reference Clocks:\n");
99	if (srds_s1 == 0x95)
100		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
101	else
102		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
103
104	return 0;
105}
106
107#ifdef CONFIG_TARGET_T1024RDB
108static void board_mux_lane(void)
109{
110	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
111	u32 srds_prtcl_s1;
112	u8 reg = CPLD_READ(misc_ctl_status);
113
114	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
115				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
116	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
117
118	if (srds_prtcl_s1 == 0x95) {
119		/* Route Lane B to PCIE */
120		CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
121	} else {
122		/* Route Lane B to SGMII */
123		CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
124	}
125	CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
126}
127#endif
128
129int board_early_init_f(void)
130{
131#if defined(CONFIG_DEEP_SLEEP)
132	if (is_warm_boot())
133		fsl_dp_disable_console();
134#endif
135
136	return 0;
137}
138
139int board_early_init_r(void)
140{
141#ifdef CFG_SYS_FLASH_BASE
142	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
143	int flash_esel = find_tlb_idx((void *)flashbase, 1);
144	/*
145	 * Remap Boot flash region to caching-inhibited
146	 * so that flash can be erased properly.
147	 */
148
149	/* Flush d-cache and invalidate i-cache of any FLASH data */
150	flush_dcache();
151	invalidate_icache();
152	if (flash_esel == -1) {
153		/* very unlikely unless something is messed up */
154		puts("Error: Could not find TLB for FLASH BASE\n");
155		flash_esel = 2;	/* give our best effort to continue */
156	} else {
157		/* invalidate existing TLB entry for flash + promjet */
158		disable_tlb(flash_esel);
159	}
160
161	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
162		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
163		0, flash_esel, BOOKE_PAGESZ_256M, 1);
164#endif
165
166#ifdef CONFIG_TARGET_T1024RDB
167	board_mux_lane();
168#endif
169
170	pci_init();
171
172	return 0;
173}
174
175#ifdef CONFIG_TARGET_T1024RDB
176void board_reset(void)
177{
178	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
179}
180#endif
181
182int misc_init_r(void)
183{
184	return 0;
185}
186
187int ft_board_setup(void *blob, struct bd_info *bd)
188{
189	phys_addr_t base;
190	phys_size_t size;
191
192	ft_cpu_setup(blob, bd);
193
194	base = env_get_bootm_low();
195	size = env_get_bootm_size();
196
197	fdt_fixup_memory(blob, (u64)base, (u64)size);
198
199#ifdef CONFIG_PCI
200	pci_of_setup(blob, bd);
201#endif
202
203	fdt_fixup_liodn(blob);
204	fsl_fdt_fixup_dr_usb(blob, bd);
205
206#ifdef CONFIG_SYS_DPAA_FMAN
207#ifndef CONFIG_DM_ETH
208	fdt_fixup_fman_ethernet(blob);
209#endif
210	fdt_fixup_board_enet(blob);
211#endif
212
213#ifdef CONFIG_TARGET_T1023RDB
214	if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
215		fdt_enable_nor(blob);
216#endif
217
218	return 0;
219}
220
221#ifdef CONFIG_TARGET_T1023RDB
222/* Enable NOR flash for RevC */
223static void fdt_enable_nor(void *blob)
224{
225	int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
226
227	if (nodeoff >= 0)
228		fdt_status_okay(blob, nodeoff);
229	else
230		printf("WARNING unable to set status for NOR\n");
231}
232
233int board_mmc_getcd(struct mmc *mmc)
234{
235	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
236	u32 val = in_be32(&pgpio->gpdat);
237
238	/* GPIO1_14, 0: eMMC, 1: SD/MMC */
239	val &= GPIO1_SD_SEL;
240
241	return val ? -1 : 1;
242}
243
244int board_mmc_getwp(struct mmc *mmc)
245{
246	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
247	u32 val = in_be32(&pgpio->gpdat);
248
249	val &= GPIO1_SD_SEL;
250
251	return val ? -1 : 0;
252}
253
254static u32 t1023rdb_ctrl(u32 ctrl_type)
255{
256	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
257	ccsr_gur_t __iomem  *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
258	u32 val;
259	u8 tmp;
260	int bus_num = I2C_PCA6408_BUS_NUM;
261
262#if CONFIG_IS_ENABLED(DM_I2C)
263	struct udevice *dev;
264	int ret;
265
266	ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
267				      1, &dev);
268	if (ret) {
269		printf("%s: Cannot find udev for a bus %d\n", __func__,
270		       bus_num);
271		return ret;
272	}
273	switch (ctrl_type) {
274	case GPIO1_SD_SEL:
275		val = in_be32(&pgpio->gpdat);
276		val |= GPIO1_SD_SEL;
277		out_be32(&pgpio->gpdat, val);
278		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
279		break;
280	case GPIO1_EMMC_SEL:
281		val = in_be32(&pgpio->gpdat);
282		val &= ~GPIO1_SD_SEL;
283		out_be32(&pgpio->gpdat, val);
284		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
285		break;
286	case GPIO3_GET_VERSION:
287		pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
288			 + GPIO3_OFFSET);
289		val = in_be32(&pgpio->gpdat);
290		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
291		if (val == 0x3) /* GPIO3_4/5 not used on RevB */
292			val = 0;
293		return val;
294	case I2C_GET_BANK:
295		dm_i2c_read(dev, 0, &tmp, 1);
296		tmp &= 0x7;
297		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
298		return tmp;
299	case I2C_SET_BANK0:
300		tmp = 0x0;
301		dm_i2c_write(dev, 1, &tmp, 1);
302		tmp = 0xf8;
303		dm_i2c_write(dev, 3, &tmp, 1);
304		/* asserting HRESET_REQ */
305		out_be32(&gur->rstcr, 0x2);
306		break;
307	case I2C_SET_BANK4:
308		tmp = 0x1;
309		dm_i2c_write(dev, 1, &tmp, 1);
310		tmp = 0xf8;
311		dm_i2c_write(dev, 3, &tmp, 1);
312		out_be32(&gur->rstcr, 0x2);
313		break;
314	default:
315		break;
316	}
317#else
318	u32 orig_bus;
319
320	orig_bus = i2c_get_bus_num();
321
322	switch (ctrl_type) {
323	case GPIO1_SD_SEL:
324		val = in_be32(&pgpio->gpdat);
325		val |= GPIO1_SD_SEL;
326		out_be32(&pgpio->gpdat, val);
327		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
328		break;
329	case GPIO1_EMMC_SEL:
330		val = in_be32(&pgpio->gpdat);
331		val &= ~GPIO1_SD_SEL;
332		out_be32(&pgpio->gpdat, val);
333		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
334		break;
335	case GPIO3_GET_VERSION:
336		pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
337			 + GPIO3_OFFSET);
338		val = in_be32(&pgpio->gpdat);
339		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
340		if (val == 0x3) /* GPIO3_4/5 not used on RevB */
341			val = 0;
342		return val;
343	case I2C_GET_BANK:
344		i2c_set_bus_num(bus_num);
345		i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
346		tmp &= 0x7;
347		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
348		i2c_set_bus_num(orig_bus);
349		return tmp;
350	case I2C_SET_BANK0:
351		i2c_set_bus_num(bus_num);
352		tmp = 0x0;
353		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
354		tmp = 0xf8;
355		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
356		/* asserting HRESET_REQ */
357		out_be32(&gur->rstcr, 0x2);
358		break;
359	case I2C_SET_BANK4:
360		i2c_set_bus_num(bus_num);
361		tmp = 0x1;
362		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
363		tmp = 0xf8;
364		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
365		out_be32(&gur->rstcr, 0x2);
366		break;
367	default:
368		break;
369	}
370#endif
371	return 0;
372}
373
374static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
375		      char *const argv[])
376{
377	if (argc < 2)
378		return CMD_RET_USAGE;
379	if (!strcmp(argv[1], "bank0"))
380		t1023rdb_ctrl(I2C_SET_BANK0);
381	else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
382		t1023rdb_ctrl(I2C_SET_BANK4);
383	else if (!strcmp(argv[1], "sd"))
384		t1023rdb_ctrl(GPIO1_SD_SEL);
385	else if (!strcmp(argv[1], "emmc"))
386		t1023rdb_ctrl(GPIO1_EMMC_SEL);
387	else
388		return CMD_RET_USAGE;
389	return 0;
390}
391
392U_BOOT_CMD(
393	switch, 2, 0, switch_cmd,
394	"for bank0/bank4/sd/emmc switch control in runtime",
395	"command (e.g. switch bank4)"
396);
397#endif
398