1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 */
5
6#include <common.h>
7#include <i2c.h>
8#include <hwconfig.h>
9#include <init.h>
10#include <log.h>
11#include <asm/global_data.h>
12#include <asm/mmu.h>
13#include <fsl_ddr_sdram.h>
14#include <fsl_ddr_dimm_params.h>
15#include <asm/fsl_law.h>
16#include <asm/mpc85xx_gpio.h>
17#include <linux/delay.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21struct board_specific_parameters {
22	u32 n_ranks;
23	u32 datarate_mhz_high;
24	u32 rank_gb;
25	u32 clk_adjust;
26	u32 wrlvl_start;
27	u32 wrlvl_ctl_2;
28	u32 wrlvl_ctl_3;
29};
30
31/*
32 * datarate_mhz_high values need to be in ascending order
33 */
34static const struct board_specific_parameters udimm0[] = {
35	/*
36	 * memory controller 0
37	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
38	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
39	 */
40	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
41	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
42	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
43	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
44	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
45	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
46	{}
47};
48
49static const struct board_specific_parameters *udimms[] = {
50	udimm0,
51};
52
53void fsl_ddr_board_options(memctl_options_t *popts,
54			   dimm_params_t *pdimm,
55			   unsigned int ctrl_num)
56{
57	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
58	ulong ddr_freq;
59	struct cpu_type *cpu = gd->arch.cpu;
60
61	if (ctrl_num > 1) {
62		printf("Not supported controller number %d\n", ctrl_num);
63		return;
64	}
65	if (!pdimm->n_ranks)
66		return;
67
68	pbsp = udimms[0];
69
70	/* Get clk_adjust according to the board ddr freqency and n_banks
71	 * specified in board_specific_parameters table.
72	 */
73	ddr_freq = get_ddr_freq(0) / 1000000;
74	while (pbsp->datarate_mhz_high) {
75		if (pbsp->n_ranks == pdimm->n_ranks &&
76		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
77			if (ddr_freq <= pbsp->datarate_mhz_high) {
78				popts->clk_adjust = pbsp->clk_adjust;
79				popts->wrlvl_start = pbsp->wrlvl_start;
80				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
81				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
82				goto found;
83			}
84			pbsp_highest = pbsp;
85		}
86		pbsp++;
87	}
88
89	if (pbsp_highest) {
90		printf("Error: board specific timing not found\n");
91		printf("for data rate %lu MT/s\n", ddr_freq);
92		printf("Trying to use the highest speed (%u) parameters\n",
93		       pbsp_highest->datarate_mhz_high);
94		popts->clk_adjust = pbsp_highest->clk_adjust;
95		popts->wrlvl_start = pbsp_highest->wrlvl_start;
96		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
97		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
98	} else {
99		panic("DIMM is not supported by this board");
100	}
101found:
102	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
103	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
104	debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
105	      pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
106	debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
107
108	/*
109	 * Factors to consider for half-strength driver enable:
110	 *	- number of DIMMs installed
111	 */
112	popts->half_strength_driver_enable = 0;
113	/*
114	 * Write leveling override
115	 */
116	popts->wrlvl_override = 1;
117	popts->wrlvl_sample = 0xf;
118
119	/*
120	 * rtt and rtt_wr override
121	 */
122	popts->rtt_override = 0;
123
124	/* Enable ZQ calibration */
125	popts->zq_en = 1;
126
127	/* DHC_EN =1, ODT = 75 Ohm */
128	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
129	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
130
131	/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
132	 * force DDR bus width to 32bit for T1023
133	 */
134	if (cpu->soc_ver == SVR_T1023)
135		popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
136
137#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
138	/* for DDR bus 32bit test on T1024 */
139	popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
140#endif
141
142#ifdef CONFIG_TARGET_T1023RDB
143	popts->wrlvl_ctl_2 = 0x07070606;
144	popts->half_strength_driver_enable = 1;
145	popts->cpo_sample = 0x43;
146#elif defined(CONFIG_TARGET_T1024RDB)
147	/* optimize cpo for erratum A-009942 */
148	popts->cpo_sample = 0x52;
149#endif
150}
151
152#ifdef CONFIG_SYS_DDR_RAW_TIMING
153/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
154dimm_params_t ddr_raw_timing = {
155	.n_ranks = 1,
156	.rank_density = 0x80000000,
157	.capacity = 0x80000000,
158	.primary_sdram_width = 32,
159	.ec_sdram_width = 8,
160	.registered_dimm = 0,
161	.mirrored_dimm = 0,
162	.n_row_addr = 15,
163	.n_col_addr = 10,
164	.bank_addr_bits = 2,
165	.bank_group_bits = 2,
166	.edc_config = 0,
167	.burst_lengths_bitmask = 0x0c,
168	.tckmin_x_ps = 938,
169	.tckmax_ps = 1500,
170	.caslat_x = 0x000DFA00,
171	.taa_ps = 13500,
172	.trcd_ps = 13500,
173	.trp_ps = 13500,
174	.tras_ps = 33000,
175	.trc_ps = 46500,
176	.trfc1_ps = 260000,
177	.trfc2_ps = 160000,
178	.trfc4_ps = 110000,
179	.tfaw_ps = 25000,
180	.trrds_ps = 3700,
181	.trrdl_ps = 5300,
182	.tccdl_ps = 5355,
183	.refresh_rate_ps = 7800000,
184	.dq_mapping[0] = 0x0,
185	.dq_mapping[1] = 0x0,
186	.dq_mapping[2] = 0x0,
187	.dq_mapping[3] = 0x0,
188	.dq_mapping[4] = 0x0,
189	.dq_mapping[5] = 0x0,
190	.dq_mapping[6] = 0x0,
191	.dq_mapping[7] = 0x0,
192	.dq_mapping[8] = 0x0,
193	.dq_mapping[9] = 0x0,
194	.dq_mapping[10] = 0x0,
195	.dq_mapping[11] = 0x0,
196	.dq_mapping[12] = 0x0,
197	.dq_mapping[13] = 0x0,
198	.dq_mapping[14] = 0x0,
199	.dq_mapping[15] = 0x0,
200	.dq_mapping[16] = 0x0,
201	.dq_mapping[17] = 0x0,
202	.dq_mapping_ors = 1,
203};
204
205int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
206		unsigned int controller_number,
207		unsigned int dimm_number)
208{
209	const char dimm_model[] = "Fixed DDR4 on board";
210
211	if (((controller_number == 0) && (dimm_number == 0)) ||
212	    ((controller_number == 1) && (dimm_number == 0))) {
213		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
214		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
215		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
216	}
217
218	return 0;
219}
220#endif
221
222#if defined(CONFIG_DEEP_SLEEP)
223void board_mem_sleep_setup(void)
224{
225	void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
226
227	/* does not provide HW signals for power management */
228	clrbits_8(cpld_base + 0x17, 0x40);
229	/* Disable MCKE isolation */
230	gpio_set_value(2, 0);
231	udelay(1);
232}
233#endif
234
235int dram_init(void)
236{
237	phys_size_t dram_size;
238
239#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
240#ifndef CONFIG_SYS_DDR_RAW_TIMING
241	puts("Initializing....using SPD\n");
242#endif
243	dram_size = fsl_ddr_sdram();
244#else
245	/* DDR has been initialised by first stage boot loader */
246	dram_size =  fsl_ddr_sdram_size();
247#endif
248	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
249	dram_size *= 0x100000;
250
251#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
252	fsl_dp_resume();
253#endif
254
255	gd->ram_size = dram_size;
256
257	return 0;
258}
259