1/* SPDX-License-Identifier: GPL-2.0+ */
2/**
3 * Copyright 2014 Freescale Semiconductor
4 *
5 */
6
7struct cpld_data {
8	u8 cpld_ver;		/* 0x00 - CPLD Major Revision Register */
9	u8 cpld_ver_sub;	/* 0x01 - CPLD Minor Revision Register */
10	u8 hw_ver;		/* 0x02 - Hardware Revision Register */
11	u8 sw_ver;		/* 0x03 - Software Revision register */
12	u8 res0[12];		/* 0x04 - 0x0F - not used */
13	u8 reset_ctl1;		/* 0x10 - Reset control Register1 */
14	u8 reset_ctl2;		/* 0x11 - Reset control Register2 */
15	u8 int_status;		/* 0x12 - Interrupt status Register */
16	u8 flash_csr;		/* 0x13 - Flash control and status register */
17	u8 fan_ctl_status;	/* 0x14 - Fan control and status register  */
18	u8 led_ctl_status;	/* 0x15 - LED control and status register */
19	u8 sfp_ctl_status;	/* 0x16 - SFP control and status register  */
20	u8 misc_ctl_status;	/* 0x17 - Miscellanies ctrl & status register*/
21	u8 boot_override;	/* 0x18 - Boot override register */
22	u8 boot_config1;	/* 0x19 - Boot config override register*/
23	u8 boot_config2;	/* 0x1A - Boot config override register*/
24};
25
26
27/* Pointer to the CPLD register set */
28
29u8 cpld_read(unsigned int reg);
30void cpld_write(unsigned int reg, u8 value);
31
32#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
33#define CPLD_WRITE(reg, value)\
34		cpld_write(offsetof(struct cpld_data, reg), value)
35
36/* CPLD on IFC */
37#define CPLD_LBMAP_MASK	 0x3F
38#define CPLD_BANK_SEL_MASK      0x07
39#define CPLD_BANK_OVERRIDE      0x40
40#define CPLD_LBMAP_ALTBANK      0x44 /* BANK OR | BANK 4 */
41#define CPLD_LBMAP_DFLTBANK     0x40 /* BANK OR | BANK 0 */
42#define CPLD_LBMAP_RESET	0xFF
43#define CPLD_LBMAP_SHIFT	0x03
44#define CPLD_BOOT_SEL	   0x80
45
46#define CPLD_PCIE_SGMII_MUX	0x80
47#define CPLD_OVERRIDE_BOOT_EN	0x01
48#define CPLD_OVERRIDE_MUX_EN	0x02 /* PCIE/2.5G-SGMII mux override enable */
49