1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 */
5
6#include <common.h>
7#include <i2c.h>
8#include <hwconfig.h>
9#include <init.h>
10#include <log.h>
11#include <asm/global_data.h>
12#include <asm/mmu.h>
13#include <fsl_ddr_sdram.h>
14#include <fsl_ddr_dimm_params.h>
15#include <asm/fsl_law.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19struct board_specific_parameters {
20	u32 n_ranks;
21	u32 datarate_mhz_high;
22	u32 clk_adjust;
23	u32 wrlvl_start;
24	u32 cpo;
25	u32 write_data_delay;
26	u32 force_2t;
27};
28
29/*
30 * This table contains all valid speeds we want to override with board
31 * specific parameters. datarate_mhz_high values need to be in ascending order
32 * for each n_ranks group.
33 *
34 * ranges for parameters:
35 *  wr_data_delay = 0-6
36 *  clk adjust = 0-8
37 *  cpo 2-0x1E (30)
38 */
39static const struct board_specific_parameters dimm0[] = {
40	/*
41	 * memory controller 0
42	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
43	 * ranks| mhz|adjst| start | delay|
44	 */
45	{2,   750,    3,     5,   0xff,    2,  0},
46	{2,  1250,    4,     6,   0xff,    2,  0},
47	{2,  1350,    5,     7,   0xff,    2,  0},
48	{2,  1666,    5,     8,   0xff,    2,  0},
49	{}
50};
51
52void fsl_ddr_board_options(memctl_options_t *popts,
53				dimm_params_t *pdimm,
54				unsigned int ctrl_num)
55{
56	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
57	ulong ddr_freq;
58
59	if (ctrl_num) {
60		printf("Wrong parameter for controller number %d", ctrl_num);
61		return;
62	}
63	if (!pdimm->n_ranks)
64		return;
65
66	pbsp = dimm0;
67
68	/*
69	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
70	 * freqency and n_banks specified in board_specific_parameters table.
71	 */
72	ddr_freq = get_ddr_freq(0) / 1000000;
73	while (pbsp->datarate_mhz_high) {
74		if (pbsp->n_ranks == pdimm->n_ranks) {
75			if (ddr_freq <= pbsp->datarate_mhz_high) {
76				popts->cpo_override = pbsp->cpo;
77				popts->write_data_delay =
78					pbsp->write_data_delay;
79				popts->clk_adjust = pbsp->clk_adjust;
80				popts->wrlvl_start = pbsp->wrlvl_start;
81				popts->twot_en = pbsp->force_2t;
82				goto found;
83			}
84			pbsp_highest = pbsp;
85		}
86		pbsp++;
87	}
88
89	if (pbsp_highest) {
90		printf("Error: board specific timing not found "
91			"for data rate %lu MT/s!\n"
92			"Trying to use the highest speed (%u) parameters\n",
93			ddr_freq, pbsp_highest->datarate_mhz_high);
94		popts->cpo_override = pbsp_highest->cpo;
95		popts->write_data_delay = pbsp_highest->write_data_delay;
96		popts->clk_adjust = pbsp_highest->clk_adjust;
97		popts->wrlvl_start = pbsp_highest->wrlvl_start;
98		popts->twot_en = pbsp_highest->force_2t;
99	} else {
100		panic("DIMM is not supported by this board");
101	}
102
103found:
104	/*
105	 * Factors to consider for half-strength driver enable:
106	 *	- number of DIMMs installed
107	 */
108	popts->half_strength_driver_enable = 0;
109	/* Write leveling override */
110	popts->wrlvl_override = 1;
111	popts->wrlvl_sample = 0xf;
112
113	/* Rtt and Rtt_WR override */
114	popts->rtt_override = 0;
115
116	/* Enable ZQ calibration */
117	popts->zq_en = 1;
118
119	/* DHC_EN =1, ODT = 60 Ohm */
120	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
121}
122
123int dram_init(void)
124{
125	phys_size_t dram_size = 0;
126
127	puts("Initializing....");
128
129	if (fsl_use_spd()) {
130		puts("using SPD\n");
131		dram_size = fsl_ddr_sdram();
132	} else {
133		puts("no SPD and fixed parameters\n");
134		return -ENXIO;
135	}
136
137	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
138	dram_size *= 0x100000;
139
140	debug("    DDR: ");
141	gd->ram_size = dram_size;
142
143	return 0;
144}
145