1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7#include <common.h> 8#include <command.h> 9#include <image.h> 10#include <init.h> 11#include <net.h> 12#include <asm/global_data.h> 13#include <asm/processor.h> 14#include <asm/mmu.h> 15#include <asm/cache.h> 16#include <asm/immap_85xx.h> 17#include <asm/io.h> 18#include <env.h> 19#include <miiphy.h> 20#include <linux/libfdt.h> 21#include <fdt_support.h> 22#include <fsl_mdio.h> 23#include <tsec.h> 24#include <mmc.h> 25#include <netdev.h> 26#include <pci.h> 27#include <asm/fsl_serdes.h> 28#include <fsl_ifc.h> 29#include <asm/fsl_pci.h> 30#include <hwconfig.h> 31#include <i2c.h> 32 33DECLARE_GLOBAL_DATA_PTR; 34 35#define GPIO4_PCIE_RESET_SET 0x08000000 36#define MUX_CPLD_CAN_UART 0x00 37#define MUX_CPLD_TDM 0x01 38#define MUX_CPLD_SPICS0_FLASH 0x00 39#define MUX_CPLD_SPICS0_SLIC 0x02 40#define PMUXCR1_IFC_MASK 0x00ffff00 41#define PMUXCR1_SDHC_MASK 0x00fff000 42#define PMUXCR1_SDHC_ENABLE 0x00555000 43 44enum { 45 MUX_TYPE_IFC, 46 MUX_TYPE_SDHC, 47 MUX_TYPE_SPIFLASH, 48 MUX_TYPE_TDM, 49 MUX_TYPE_CAN, 50 MUX_TYPE_CS0_NOR, 51 MUX_TYPE_CS0_NAND, 52}; 53 54enum { 55 I2C_READ_BANK, 56 I2C_READ_PCB_VER, 57}; 58 59static uint sd_ifc_mux; 60 61struct cpld_data { 62 u8 cpld_ver; /* cpld revision */ 63#if defined(CONFIG_TARGET_P1010RDB_PA) 64 u8 pcba_ver; /* pcb revision number */ 65 u8 twindie_ddr3; 66 u8 res1[6]; 67 u8 bank_sel; /* NOR Flash bank */ 68 u8 res2[5]; 69 u8 usb2_sel; 70 u8 res3[1]; 71 u8 porsw_sel; 72 u8 tdm_can_sel; 73 u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */ 74 u8 por0; /* POR Options */ 75 u8 por1; /* POR Options */ 76 u8 por2; /* POR Options */ 77 u8 por3; /* POR Options */ 78#elif defined(CONFIG_TARGET_P1010RDB_PB) 79 u8 rom_loc; 80#endif 81}; 82 83int board_early_init_f(void) 84{ 85 ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); 86 struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; 87 /* Clock configuration to access CPLD using IFC(GPCM) */ 88 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 89 /* 90 * Reset PCIe slots via GPIO4 91 */ 92 setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET); 93 setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET); 94 95 return 0; 96} 97 98int board_early_init_r(void) 99{ 100 const unsigned int flashbase = CFG_SYS_FLASH_BASE; 101 int flash_esel = find_tlb_idx((void *)flashbase, 1); 102 103 /* 104 * Remap Boot flash region to caching-inhibited 105 * so that flash can be erased properly. 106 */ 107 108 /* Flush d-cache and invalidate i-cache of any FLASH data */ 109 flush_dcache(); 110 invalidate_icache(); 111 112 if (flash_esel == -1) { 113 /* very unlikely unless something is messed up */ 114 puts("Error: Could not find TLB for FLASH BASE\n"); 115 flash_esel = 2; /* give our best effort to continue */ 116 } else { 117 /* invalidate existing TLB entry for flash */ 118 disable_tlb(flash_esel); 119 } 120 121 set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, 122 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 123 0, flash_esel, BOOKE_PAGESZ_16M, 1); 124 125 set_tlb(1, flashbase + 0x1000000, 126 CFG_SYS_FLASH_BASE_PHYS + 0x1000000, 127 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 128 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); 129 return 0; 130} 131 132int config_board_mux(int ctrl_type) 133{ 134 ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 135 u8 tmp; 136 137#if CONFIG_IS_ENABLED(DM_I2C) 138 struct udevice *dev; 139 int ret; 140#if defined(CONFIG_TARGET_P1010RDB_PA) 141 struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); 142 143 ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, 144 I2C_PCA9557_ADDR1, 1, &dev); 145 if (ret) { 146 printf("%s: Cannot find udev for a bus %d\n", 147 __func__, I2C_PCA9557_BUS_NUM); 148 return ret; 149 } 150 switch (ctrl_type) { 151 case MUX_TYPE_IFC: 152 tmp = 0xf0; 153 dm_i2c_write(dev, 3, &tmp, 1); 154 tmp = 0x01; 155 dm_i2c_write(dev, 1, &tmp, 1); 156 sd_ifc_mux = MUX_TYPE_IFC; 157 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); 158 break; 159 case MUX_TYPE_SDHC: 160 tmp = 0xf0; 161 dm_i2c_write(dev, 3, &tmp, 1); 162 tmp = 0x05; 163 dm_i2c_write(dev, 1, &tmp, 1); 164 sd_ifc_mux = MUX_TYPE_SDHC; 165 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, 166 PMUXCR1_SDHC_ENABLE); 167 break; 168 case MUX_TYPE_SPIFLASH: 169 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); 170 break; 171 case MUX_TYPE_TDM: 172 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); 173 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); 174 break; 175 case MUX_TYPE_CAN: 176 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); 177 break; 178 default: 179 break; 180 } 181#elif defined(CONFIG_TARGET_P1010RDB_PB) 182 ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, 183 I2C_PCA9557_ADDR2, 1, &dev); 184 if (ret) { 185 printf("%s: Cannot find udev for a bus %d\n", 186 __func__, I2C_PCA9557_BUS_NUM); 187 return ret; 188 } 189 switch (ctrl_type) { 190 case MUX_TYPE_IFC: 191 dm_i2c_read(dev, 0, &tmp, 1); 192 clrbits_8(&tmp, 0x04); 193 dm_i2c_write(dev, 1, &tmp, 1); 194 dm_i2c_read(dev, 3, &tmp, 1); 195 clrbits_8(&tmp, 0x04); 196 dm_i2c_write(dev, 3, &tmp, 1); 197 sd_ifc_mux = MUX_TYPE_IFC; 198 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); 199 break; 200 case MUX_TYPE_SDHC: 201 dm_i2c_read(dev, 0, &tmp, 1); 202 setbits_8(&tmp, 0x04); 203 dm_i2c_write(dev, 1, &tmp, 1); 204 dm_i2c_read(dev, 3, &tmp, 1); 205 clrbits_8(&tmp, 0x04); 206 dm_i2c_write(dev, 3, &tmp, 1); 207 sd_ifc_mux = MUX_TYPE_SDHC; 208 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, 209 PMUXCR1_SDHC_ENABLE); 210 break; 211 case MUX_TYPE_SPIFLASH: 212 dm_i2c_read(dev, 0, &tmp, 1); 213 clrbits_8(&tmp, 0x80); 214 dm_i2c_write(dev, 1, &tmp, 1); 215 dm_i2c_read(dev, 3, &tmp, 1); 216 clrbits_8(&tmp, 0x80); 217 dm_i2c_write(dev, 3, &tmp, 1); 218 break; 219 case MUX_TYPE_TDM: 220 dm_i2c_read(dev, 0, &tmp, 1); 221 setbits_8(&tmp, 0x82); 222 dm_i2c_write(dev, 1, &tmp, 1); 223 dm_i2c_read(dev, 3, &tmp, 1); 224 clrbits_8(&tmp, 0x82); 225 dm_i2c_write(dev, 3, &tmp, 1); 226 break; 227 case MUX_TYPE_CAN: 228 dm_i2c_read(dev, 0, &tmp, 1); 229 clrbits_8(&tmp, 0x02); 230 dm_i2c_write(dev, 1, &tmp, 1); 231 dm_i2c_read(dev, 3, &tmp, 1); 232 clrbits_8(&tmp, 0x02); 233 dm_i2c_write(dev, 3, &tmp, 1); 234 break; 235 case MUX_TYPE_CS0_NOR: 236 dm_i2c_read(dev, 0, &tmp, 1); 237 clrbits_8(&tmp, 0x08); 238 dm_i2c_write(dev, 1, &tmp, 1); 239 dm_i2c_read(dev, 3, &tmp, 1); 240 clrbits_8(&tmp, 0x08); 241 dm_i2c_write(dev, 3, &tmp, 1); 242 break; 243 case MUX_TYPE_CS0_NAND: 244 dm_i2c_read(dev, 0, &tmp, 1); 245 setbits_8(&tmp, 0x08); 246 dm_i2c_write(dev, 1, &tmp, 1); 247 dm_i2c_read(dev, 3, &tmp, 1); 248 clrbits_8(&tmp, 0x08); 249 dm_i2c_write(dev, 3, &tmp, 1); 250 break; 251 default: 252 break; 253 } 254#endif 255#else 256#if defined(CONFIG_TARGET_P1010RDB_PA) 257 struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); 258 259 switch (ctrl_type) { 260 case MUX_TYPE_IFC: 261 i2c_set_bus_num(I2C_PCA9557_BUS_NUM); 262 tmp = 0xf0; 263 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); 264 tmp = 0x01; 265 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); 266 sd_ifc_mux = MUX_TYPE_IFC; 267 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); 268 break; 269 case MUX_TYPE_SDHC: 270 i2c_set_bus_num(I2C_PCA9557_BUS_NUM); 271 tmp = 0xf0; 272 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); 273 tmp = 0x05; 274 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); 275 sd_ifc_mux = MUX_TYPE_SDHC; 276 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, 277 PMUXCR1_SDHC_ENABLE); 278 break; 279 case MUX_TYPE_SPIFLASH: 280 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); 281 break; 282 case MUX_TYPE_TDM: 283 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); 284 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); 285 break; 286 case MUX_TYPE_CAN: 287 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); 288 break; 289 default: 290 break; 291 } 292#elif defined(CONFIG_TARGET_P1010RDB_PB) 293 uint orig_bus = i2c_get_bus_num(); 294 i2c_set_bus_num(I2C_PCA9557_BUS_NUM); 295 296 switch (ctrl_type) { 297 case MUX_TYPE_IFC: 298 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); 299 clrbits_8(&tmp, 0x04); 300 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); 301 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 302 clrbits_8(&tmp, 0x04); 303 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 304 sd_ifc_mux = MUX_TYPE_IFC; 305 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); 306 break; 307 case MUX_TYPE_SDHC: 308 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); 309 setbits_8(&tmp, 0x04); 310 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); 311 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 312 clrbits_8(&tmp, 0x04); 313 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 314 sd_ifc_mux = MUX_TYPE_SDHC; 315 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, 316 PMUXCR1_SDHC_ENABLE); 317 break; 318 case MUX_TYPE_SPIFLASH: 319 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); 320 clrbits_8(&tmp, 0x80); 321 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); 322 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 323 clrbits_8(&tmp, 0x80); 324 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 325 break; 326 case MUX_TYPE_TDM: 327 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); 328 setbits_8(&tmp, 0x82); 329 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); 330 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 331 clrbits_8(&tmp, 0x82); 332 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 333 break; 334 case MUX_TYPE_CAN: 335 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); 336 clrbits_8(&tmp, 0x02); 337 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); 338 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 339 clrbits_8(&tmp, 0x02); 340 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 341 break; 342 case MUX_TYPE_CS0_NOR: 343 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); 344 clrbits_8(&tmp, 0x08); 345 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); 346 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 347 clrbits_8(&tmp, 0x08); 348 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 349 break; 350 case MUX_TYPE_CS0_NAND: 351 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); 352 setbits_8(&tmp, 0x08); 353 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); 354 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 355 clrbits_8(&tmp, 0x08); 356 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); 357 break; 358 default: 359 break; 360 } 361 i2c_set_bus_num(orig_bus); 362#endif 363#endif 364 return 0; 365} 366 367#ifdef CONFIG_TARGET_P1010RDB_PB 368int i2c_pca9557_read(int type) 369{ 370 u8 val; 371 int bus_num = I2C_PCA9557_BUS_NUM; 372 373#if CONFIG_IS_ENABLED(DM_I2C) 374 struct udevice *dev; 375 int ret; 376 377 ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev); 378 if (ret) { 379 printf("%s: Cannot find udev for a bus %d\n", 380 __func__, bus_num); 381 return ret; 382 } 383 dm_i2c_read(dev, 0, &val, 1); 384#else 385 i2c_set_bus_num(bus_num); 386 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); 387#endif 388 389 switch (type) { 390 case I2C_READ_BANK: 391 val = (val & 0x10) >> 4; 392 break; 393 case I2C_READ_PCB_VER: 394 val = ((val & 0x60) >> 5) + 1; 395 break; 396 default: 397 break; 398 } 399 400 return val; 401} 402#endif 403 404int checkboard(void) 405{ 406 struct cpu_type *cpu; 407 struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); 408 u8 val; 409 410 cpu = gd->arch.cpu; 411#if defined(CONFIG_TARGET_P1010RDB_PA) 412 printf("Board: %sRDB-PA, ", cpu->name); 413#elif defined(CONFIG_TARGET_P1010RDB_PB) 414 printf("Board: %sRDB-PB, ", cpu->name); 415#if CONFIG_IS_ENABLED(DM_I2C) 416 struct udevice *dev; 417 int ret; 418 419 ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2, 420 1, &dev); 421 if (ret) { 422 printf("%s: Cannot find udev for a bus %d\n", __func__, 423 I2C_PCA9557_BUS_NUM); 424 return ret; 425 } 426 val = 0x0; /* no polarity inversion */ 427 dm_i2c_write(dev, 2, &val, 1); 428#else 429 i2c_set_bus_num(I2C_PCA9557_BUS_NUM); 430 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 431 val = 0x0; /* no polarity inversion */ 432 i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); 433#endif 434#endif 435 436#ifdef CONFIG_SDCARD 437 /* switch to IFC to read info from CPLD */ 438 config_board_mux(MUX_TYPE_IFC); 439#endif 440 441#if defined(CONFIG_TARGET_P1010RDB_PA) 442 val = (in_8(&cpld_data->pcba_ver) & 0xf); 443 printf("PCB: v%x.0\n", val); 444#elif defined(CONFIG_TARGET_P1010RDB_PB) 445 val = in_8(&cpld_data->cpld_ver); 446 printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); 447 printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); 448 val = in_8(&cpld_data->rom_loc) & 0xf; 449 puts("Boot from: "); 450 switch (val) { 451 case 0xf: 452 config_board_mux(MUX_TYPE_CS0_NOR); 453 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK)); 454 break; 455 case 0xe: 456 puts("SDHC\n"); 457 val = 0x60; /* set pca9557 pin input/output */ 458#if CONFIG_IS_ENABLED(DM_I2C) 459 dm_i2c_write(dev, 3, &val, 1); 460#else 461 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); 462#endif 463 break; 464 case 0x5: 465 config_board_mux(MUX_TYPE_IFC); 466 config_board_mux(MUX_TYPE_CS0_NAND); 467 puts("NAND\n"); 468 break; 469 case 0x6: 470 config_board_mux(MUX_TYPE_IFC); 471 puts("SPI\n"); 472 break; 473 default: 474 puts("unknown\n"); 475 break; 476 } 477#endif 478 return 0; 479} 480 481#if defined(CONFIG_OF_BOARD_SETUP) 482void fdt_del_flexcan(void *blob) 483{ 484 int nodeoff = 0; 485 486 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 487 "fsl,p1010-flexcan")) >= 0) { 488 fdt_del_node(blob, nodeoff); 489 } 490} 491 492void fdt_del_spi_flash(void *blob) 493{ 494 int nodeoff = 0; 495 496 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 497 "spansion,s25sl12801")) >= 0) { 498 fdt_del_node(blob, nodeoff); 499 } 500} 501 502void fdt_del_spi_slic(void *blob) 503{ 504 int nodeoff = 0; 505 506 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 507 "zarlink,le88266")) >= 0) { 508 fdt_del_node(blob, nodeoff); 509 } 510} 511 512void fdt_del_tdm(void *blob) 513{ 514 int nodeoff = 0; 515 516 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 517 "fsl,starlite-tdm")) >= 0) { 518 fdt_del_node(blob, nodeoff); 519 } 520} 521 522void fdt_del_sdhc(void *blob) 523{ 524 int nodeoff = 0; 525 526 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 527 "fsl,esdhc")) >= 0) { 528 fdt_del_node(blob, nodeoff); 529 } 530} 531 532void fdt_del_ifc(void *blob) 533{ 534 int nodeoff = 0; 535 536 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 537 "fsl,ifc")) >= 0) { 538 fdt_del_node(blob, nodeoff); 539 } 540} 541 542void fdt_disable_uart1(void *blob) 543{ 544 int nodeoff; 545 546 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", 547 CFG_SYS_NS16550_COM2); 548 549 if (nodeoff > 0) { 550 fdt_status_disabled(blob, nodeoff); 551 } else { 552 printf("WARNING unable to set status for fsl,ns16550 " 553 "uart1: %s\n", fdt_strerror(nodeoff)); 554 } 555} 556 557int ft_board_setup(void *blob, struct bd_info *bd) 558{ 559 phys_addr_t base; 560 phys_size_t size; 561 struct cpu_type *cpu; 562 563 cpu = gd->arch.cpu; 564 565 ft_cpu_setup(blob, bd); 566 567 base = env_get_bootm_low(); 568 size = env_get_bootm_size(); 569 570 fdt_fixup_memory(blob, (u64)base, (u64)size); 571 572#if defined(CONFIG_HAS_FSL_DR_USB) 573 fsl_fdt_fixup_dr_usb(blob, bd); 574#endif 575 576 /* P1014 and it's derivatives don't support CAN and eTSEC3 */ 577 if (cpu->soc_ver == SVR_P1014) { 578 fdt_del_flexcan(blob); 579 fdt_del_node_and_alias(blob, "ethernet2"); 580 } 581 582 /* Delete IFC node as IFC pins are multiplexing with SDHC */ 583 if (sd_ifc_mux != MUX_TYPE_IFC) 584 fdt_del_ifc(blob); 585 else 586 fdt_del_sdhc(blob); 587 588 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { 589 fdt_del_tdm(blob); 590 fdt_del_spi_slic(blob); 591 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { 592 fdt_del_flexcan(blob); 593 fdt_del_spi_flash(blob); 594 fdt_disable_uart1(blob); 595 } else { 596 /* 597 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" 598 * explicitly, defaultly spi_cs_sel to spi-flash instead of 599 * to tdm/slic. 600 */ 601 fdt_del_tdm(blob); 602 fdt_del_flexcan(blob); 603 fdt_disable_uart1(blob); 604 } 605 606 return 0; 607} 608#endif 609 610#ifdef CONFIG_SDCARD 611int board_mmc_init(struct bd_info *bis) 612{ 613 config_board_mux(MUX_TYPE_SDHC); 614 return -1; 615} 616#else 617void board_reset(void) 618{ 619 /* mux to IFC to enable CPLD for reset */ 620 if (sd_ifc_mux != MUX_TYPE_IFC) 621 config_board_mux(MUX_TYPE_IFC); 622} 623#endif 624 625 626int misc_init_r(void) 627{ 628 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 629 630 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { 631 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | 632 MPC85xx_PMUXCR_CAN1_UART | 633 MPC85xx_PMUXCR_CAN2_TDM | 634 MPC85xx_PMUXCR_CAN2_UART); 635 config_board_mux(MUX_TYPE_CAN); 636 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { 637 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | 638 MPC85xx_PMUXCR_CAN1_UART); 639 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | 640 MPC85xx_PMUXCR_CAN1_TDM); 641 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); 642 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); 643 config_board_mux(MUX_TYPE_TDM); 644 } else { 645 /* defaultly spi_cs_sel to flash */ 646 config_board_mux(MUX_TYPE_SPIFLASH); 647 } 648 649 if (hwconfig("esdhc")) 650 config_board_mux(MUX_TYPE_SDHC); 651 else if (hwconfig("ifc")) 652 config_board_mux(MUX_TYPE_IFC); 653 654#ifdef CONFIG_TARGET_P1010RDB_PB 655 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); 656#endif 657 return 0; 658} 659 660#ifndef CONFIG_SPL_BUILD 661static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc, 662 char *const argv[]) 663{ 664 if (argc < 2) 665 return CMD_RET_USAGE; 666 if (strcmp(argv[1], "ifc") == 0) 667 config_board_mux(MUX_TYPE_IFC); 668 else if (strcmp(argv[1], "sdhc") == 0) 669 config_board_mux(MUX_TYPE_SDHC); 670 else 671 return CMD_RET_USAGE; 672 return 0; 673} 674 675U_BOOT_CMD( 676 mux, 2, 0, pin_mux_cmd, 677 "configure multiplexing pin for IFC/SDHC bus in runtime", 678 "bus_type (e.g. mux sdhc)" 679); 680#endif 681