1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2014 Freescale Semiconductor, Inc. 4 */ 5 6#include <config.h> 7 8/* image version */ 9 10IMAGE_VERSION 2 11 12/* 13 * Boot Device : one of 14 * spi/sd/nand/onenand, qspi/nor 15 */ 16 17BOOT_FROM sd 18 19/* 20 * Secure boot support 21 */ 22#ifdef CONFIG_IMX_HAB 23CSF CONFIG_CSF_SIZE 24#endif 25 26/* 27 * Device Configuration Data (DCD) 28 * 29 * Each entry must have the format: 30 * Addr-type Address Value 31 * 32 * where: 33 * Addr-type register length (1,2 or 4 bytes) 34 * Address absolute address of the register 35 * value value to be stored in the register 36 */ 37 38/* Enable all clocks */ 39DATA 4 0x020c4068 0xffffffff 40DATA 4 0x020c406c 0xffffffff 41DATA 4 0x020c4070 0xffffffff 42DATA 4 0x020c4074 0xffffffff 43DATA 4 0x020c4078 0xffffffff 44DATA 4 0x020c407c 0xffffffff 45DATA 4 0x020c4080 0xffffffff 46DATA 4 0x020c4084 0xffffffff 47 48/* IOMUX - DDR IO Type */ 49DATA 4 0x020e0618 0x000c0000 50DATA 4 0x020e05fc 0x00000000 51 52/* Clock */ 53DATA 4 0x020e032c 0x00000030 54 55/* Address */ 56DATA 4 0x020e0300 0x00000020 57DATA 4 0x020e02fc 0x00000020 58DATA 4 0x020e05f4 0x00000020 59 60/* Control */ 61DATA 4 0x020e0340 0x00000020 62 63DATA 4 0x020e0320 0x00000000 64DATA 4 0x020e0310 0x00000020 65DATA 4 0x020e0314 0x00000020 66DATA 4 0x020e0614 0x00000020 67 68/* Data Strobe */ 69DATA 4 0x020e05f8 0x00020000 70DATA 4 0x020e0330 0x00000028 71DATA 4 0x020e0334 0x00000028 72DATA 4 0x020e0338 0x00000028 73DATA 4 0x020e033c 0x00000028 74 75/* Data */ 76DATA 4 0x020e0608 0x00020000 77DATA 4 0x020e060c 0x00000028 78DATA 4 0x020e0610 0x00000028 79DATA 4 0x020e061c 0x00000028 80DATA 4 0x020e0620 0x00000028 81DATA 4 0x020e02ec 0x00000028 82DATA 4 0x020e02f0 0x00000028 83DATA 4 0x020e02f4 0x00000028 84DATA 4 0x020e02f8 0x00000028 85 86/* Calibrations - ZQ */ 87DATA 4 0x021b0800 0xa1390003 88 89/* Write leveling */ 90DATA 4 0x021b080c 0x00290025 91DATA 4 0x021b0810 0x00220022 92 93/* DQS Read Gate */ 94DATA 4 0x021b083c 0x41480144 95DATA 4 0x021b0840 0x01340130 96 97/* Read/Write Delay */ 98DATA 4 0x021b0848 0x3C3E4244 99DATA 4 0x021b0850 0x34363638 100 101/* Read data bit delay */ 102DATA 4 0x021b081c 0x33333333 103DATA 4 0x021b0820 0x33333333 104DATA 4 0x021b0824 0x33333333 105DATA 4 0x021b0828 0x33333333 106 107/* Complete calibration by forced measurement */ 108DATA 4 0x021b08b8 0x00000800 109 110/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ 111DATA 4 0x021b0004 0x0002002d 112DATA 4 0x021b0008 0x00333030 113DATA 4 0x021b000c 0x676b52f3 114DATA 4 0x021b0010 0xb66d8b63 115DATA 4 0x021b0014 0x01ff00db 116DATA 4 0x021b0018 0x00011740 117DATA 4 0x021b001c 0x00008000 118DATA 4 0x021b002c 0x000026d2 119DATA 4 0x021b0030 0x006b1023 120DATA 4 0x021b0040 0x0000005f 121DATA 4 0x021b0000 0x84190000 122 123/* Initialize MT41K256M16HA-125 - MR2 */ 124DATA 4 0x021b001c 0x04008032 125/* MR3 */ 126DATA 4 0x021b001c 0x00008033 127/* MR1 */ 128DATA 4 0x021b001c 0x00048031 129/* MR0 */ 130DATA 4 0x021b001c 0x05208030 131/* DDR device ZQ calibration */ 132DATA 4 0x021b001c 0x04008040 133 134/* Final DDR setup, before operation start */ 135DATA 4 0x021b0020 0x00000800 136DATA 4 0x021b0818 0x00011117 137DATA 4 0x021b001c 0x00000000 138