1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2015 Freescale Semiconductor
4 * Copyright 2017, 2021 NXP
5 */
6#include <common.h>
7#include <clock_legacy.h>
8#include <display_options.h>
9#include <env.h>
10#include <init.h>
11#include <malloc.h>
12#include <errno.h>
13#include <netdev.h>
14#include <fsl_ifc.h>
15#include <fsl_ddr.h>
16#include <asm/global_data.h>
17#include <asm/io.h>
18#include <hwconfig.h>
19#include <fdt_support.h>
20#include <linux/libfdt.h>
21#include <fsl-mc/fsl_mc.h>
22#include <env_internal.h>
23#include <efi_loader.h>
24#include <i2c.h>
25#include <asm/arch/mmu.h>
26#include <asm/arch/soc.h>
27#include <asm/arch-fsl-layerscape/fsl_icid.h>
28#include "../common/i2c_mux.h"
29
30#ifdef CONFIG_FSL_QIXIS
31#include "../common/qixis.h"
32#include "ls2080ardb_qixis.h"
33#endif
34#include "../common/vid.h"
35
36#define CORTINA_FW_ADDR_IFCNOR			0x580980000
37#define CORTINA_FW_ADDR_IFCNOR_ALTBANK	0x584980000
38#define CORTINA_FW_ADDR_QSPI			0x980000
39#define PIN_MUX_SEL_SDHC	0x00
40#define PIN_MUX_SEL_DSPI	0x0a
41
42#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
43DECLARE_GLOBAL_DATA_PTR;
44
45enum {
46	MUX_TYPE_SDHC,
47	MUX_TYPE_DSPI,
48};
49
50#ifdef CONFIG_VID
51u16 soc_get_fuse_vid(int vid_index)
52{
53	static const u16 vdd[32] = {
54		10500,
55		0,      /* reserved */
56		9750,
57		0,      /* reserved */
58		9500,
59		0,      /* reserved */
60		0,      /* reserved */
61		0,      /* reserved */
62		9000,   /* reserved */
63		0,      /* reserved */
64		0,      /* reserved */
65		0,      /* reserved */
66		0,      /* reserved */
67		0,      /* reserved */
68		0,      /* reserved */
69		0,      /* reserved */
70		10000,  /* 1.0000V */
71		0,      /* reserved */
72		10250,
73		0,      /* reserved */
74		10500,
75		0,      /* reserved */
76		0,      /* reserved */
77		0,      /* reserved */
78		0,      /* reserved */
79		0,      /* reserved */
80		0,      /* reserved */
81		0,      /* reserved */
82		0,      /* reserved */
83		0,      /* reserved */
84		0,      /* reserved */
85		0,      /* reserved */
86	};
87
88	return vdd[vid_index];
89};
90#endif
91
92unsigned long long get_qixis_addr(void)
93{
94	unsigned long long addr;
95
96	if (gd->flags & GD_FLG_RELOC)
97		addr = QIXIS_BASE_PHYS;
98	else
99		addr = QIXIS_BASE_PHYS_EARLY;
100
101	/*
102	 * IFC address under 256MB is mapped to 0x30000000, any address above
103	 * is mapped to 0x5_10000000 up to 4GB.
104	 */
105	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
106
107	return addr;
108}
109
110int checkboard(void)
111{
112#ifdef CONFIG_FSL_QIXIS
113	u8 sw;
114#endif
115	char buf[15];
116
117	cpu_name(buf);
118	printf("Board: %s-RDB, ", buf);
119
120#ifdef CONFIG_TARGET_LS2081ARDB
121#ifdef CONFIG_FSL_QIXIS
122	sw = QIXIS_READ(arch);
123	printf("Board version: %c, ", (sw & 0xf) + 'A');
124
125	sw = QIXIS_READ(brdcfg[0]);
126	sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
127	switch (sw) {
128	case 0:
129		puts("boot from QSPI DEV#0\n");
130		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
131		break;
132	case 1:
133		puts("boot from QSPI DEV#1\n");
134		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
135		break;
136	case 2:
137		puts("boot from QSPI EMU\n");
138		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
139		break;
140	case 3:
141		puts("boot from QSPI EMU\n");
142		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
143		break;
144	case 4:
145		puts("boot from QSPI DEV#0\n");
146		puts("QSPI_CSA_1 mapped to QSPI EMU\n");
147		break;
148	default:
149		printf("invalid setting of SW%u\n", sw);
150		break;
151	}
152	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
153#endif
154	puts("SERDES1 Reference : ");
155	printf("Clock1 = 100MHz ");
156	printf("Clock2 = 161.13MHz");
157#else
158#ifdef CONFIG_FSL_QIXIS
159	sw = QIXIS_READ(arch);
160	printf("Board Arch: V%d, ", sw >> 4);
161	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
162
163	sw = QIXIS_READ(brdcfg[0]);
164	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
165
166	if (sw < 0x8)
167		printf("vBank: %d\n", sw);
168	else if (sw == 0x9)
169		puts("NAND\n");
170	else
171		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
172
173	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
174#endif
175	puts("SERDES1 Reference : ");
176	printf("Clock1 = 156.25MHz ");
177	printf("Clock2 = 156.25MHz");
178#endif
179
180	puts("\nSERDES2 Reference : ");
181	printf("Clock1 = 100MHz ");
182	printf("Clock2 = 100MHz\n");
183
184	return 0;
185}
186
187unsigned long get_board_sys_clk(void)
188{
189#ifdef CONFIG_FSL_QIXIS
190	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
191
192	switch (sysclk_conf & 0x0F) {
193	case QIXIS_SYSCLK_83:
194		return 83333333;
195	case QIXIS_SYSCLK_100:
196		return 100000000;
197	case QIXIS_SYSCLK_125:
198		return 125000000;
199	case QIXIS_SYSCLK_133:
200		return 133333333;
201	case QIXIS_SYSCLK_150:
202		return 150000000;
203	case QIXIS_SYSCLK_160:
204		return 160000000;
205	case QIXIS_SYSCLK_166:
206		return 166666666;
207	}
208#endif
209	return 100000000;
210}
211
212int i2c_multiplexer_select_vid_channel(u8 channel)
213{
214	return select_i2c_ch_pca9547(channel, 0);
215}
216
217int config_board_mux(int ctrl_type)
218{
219#ifdef CONFIG_FSL_QIXIS
220	u8 reg5;
221
222	reg5 = QIXIS_READ(brdcfg[5]);
223
224	switch (ctrl_type) {
225	case MUX_TYPE_SDHC:
226		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
227		break;
228	case MUX_TYPE_DSPI:
229		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
230		break;
231	default:
232		printf("Wrong mux interface type\n");
233		return -1;
234	}
235
236	QIXIS_WRITE(brdcfg[5], reg5);
237#endif
238	return 0;
239}
240
241ulong *cs4340_get_fw_addr(void)
242{
243#ifdef CONFIG_TFABOOT
244	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
245	u32 svr = gur_in32(&gur->svr);
246#endif
247	ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
248
249#ifdef CONFIG_TFABOOT
250	/* LS2088A TFA boot */
251	if (SVR_SOC_VER(svr) == SVR_LS2088A) {
252		enum boot_src src = get_boot_src();
253		u8 sw;
254
255		switch (src) {
256		case BOOT_SOURCE_IFC_NOR:
257			sw = QIXIS_READ(brdcfg[0]);
258			sw = (sw & 0x0f);
259			if (sw == 0)
260				cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
261			else if (sw == 4)
262				cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
263			break;
264		case BOOT_SOURCE_QSPI_NOR:
265			/* Only one bank in QSPI */
266			cortina_fw_addr = CORTINA_FW_ADDR_QSPI;
267			break;
268		default:
269			printf("WARNING: Boot source not found\n");
270		}
271	}
272#endif
273	return (ulong *)cortina_fw_addr;
274}
275
276int board_init(void)
277{
278#ifdef CONFIG_FSL_MC_ENET
279	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
280#endif
281
282	init_final_memctl_regs();
283
284	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
285
286#ifdef CONFIG_FSL_QIXIS
287	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
288#endif
289
290#ifdef CONFIG_FSL_MC_ENET
291	/* invert AQR405 IRQ pins polarity */
292	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
293#endif
294
295#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
296	pci_init();
297#endif
298
299	return 0;
300}
301
302int board_early_init_f(void)
303{
304#if defined(CONFIG_SYS_I2C_EARLY_INIT)
305	i2c_early_init_f();
306#endif
307	fsl_lsch3_early_init_f();
308	return 0;
309}
310
311int misc_init_r(void)
312{
313	char *env_hwconfig;
314	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
315	u32 val;
316	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
317	u32 svr = gur_in32(&gur->svr);
318
319	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
320
321	env_hwconfig = env_get("hwconfig");
322
323	if (hwconfig_f("dspi", env_hwconfig) &&
324	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
325		config_board_mux(MUX_TYPE_DSPI);
326	else
327		config_board_mux(MUX_TYPE_SDHC);
328
329	/*
330	 * LS2081ARDB RevF board has smart voltage translator
331	 * which needs to be programmed to enable high speed SD interface
332	 * by setting GPIO4_10 output to zero
333	 */
334#ifdef CONFIG_TARGET_LS2081ARDB
335		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
336					    in_le32(GPIO4_GPDIR_ADDR)));
337		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
338					    in_le32(GPIO4_GPDAT_ADDR)));
339#endif
340	if (hwconfig("sdhc"))
341		config_board_mux(MUX_TYPE_SDHC);
342
343	if (adjust_vdd(0))
344		printf("Warning: Adjusting core voltage failed.\n");
345	/*
346	 * Default value of board env is based on filename which is
347	 * ls2080ardb. Modify board env for other supported SoCs
348	 */
349	if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
350	    (SVR_SOC_VER(svr) == SVR_LS2048A))
351		env_set("board", "ls2088ardb");
352	else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
353	    (SVR_SOC_VER(svr) == SVR_LS2041A))
354		env_set("board", "ls2081ardb");
355
356	return 0;
357}
358
359void detail_board_ddr_info(void)
360{
361	puts("\nDDR    ");
362	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
363	print_ddr_info(0);
364#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
365	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
366		puts("\nDP-DDR ");
367		print_size(gd->bd->bi_dram[2].size, "");
368		print_ddr_info(CONFIG_DP_DDR_CTRL);
369	}
370#endif
371}
372
373#ifdef CONFIG_FSL_MC_ENET
374void fdt_fixup_board_enet(void *fdt)
375{
376	int offset;
377
378	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
379
380	if (offset < 0)
381		offset = fdt_path_offset(fdt, "/fsl-mc");
382
383	if (offset < 0) {
384		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
385		       __func__, offset);
386		return;
387	}
388
389	if (get_mc_boot_status() == 0 &&
390	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
391		fdt_status_okay(fdt, offset);
392	else
393		fdt_status_fail(fdt, offset);
394}
395
396void board_quiesce_devices(void)
397{
398	fsl_mc_ldpaa_exit(gd->bd);
399}
400#endif
401
402#ifdef CONFIG_OF_BOARD_SETUP
403void fsl_fdt_fixup_flash(void *fdt)
404{
405	int offset;
406#ifdef CONFIG_TFABOOT
407	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
408	u32 val;
409#endif
410
411/*
412 * IFC and QSPI are muxed on board.
413 * So disable IFC node in dts if QSPI is enabled or
414 * disable QSPI node in dts in case QSPI is not enabled.
415 */
416#ifdef CONFIG_TFABOOT
417	enum boot_src src = get_boot_src();
418	bool disable_ifc = false;
419
420	switch (src) {
421	case BOOT_SOURCE_IFC_NOR:
422		disable_ifc = false;
423		break;
424	case BOOT_SOURCE_QSPI_NOR:
425		disable_ifc = true;
426		break;
427	default:
428		val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
429		if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
430			disable_ifc = true;
431		break;
432	}
433
434	if (disable_ifc) {
435		offset = fdt_path_offset(fdt, "/soc/ifc");
436
437		if (offset < 0)
438			offset = fdt_path_offset(fdt, "/ifc");
439	} else {
440		offset = fdt_path_offset(fdt, "/soc/quadspi");
441
442		if (offset < 0)
443			offset = fdt_path_offset(fdt, "/quadspi");
444	}
445
446#else
447#ifdef CONFIG_FSL_QSPI
448	offset = fdt_path_offset(fdt, "/soc/ifc");
449
450	if (offset < 0)
451		offset = fdt_path_offset(fdt, "/ifc");
452#else
453	offset = fdt_path_offset(fdt, "/soc/quadspi");
454
455	if (offset < 0)
456		offset = fdt_path_offset(fdt, "/quadspi");
457#endif
458#endif
459
460	if (offset < 0)
461		return;
462
463	fdt_status_disabled(fdt, offset);
464}
465
466int ft_board_setup(void *blob, struct bd_info *bd)
467{
468	int i;
469	u16 mc_memory_bank = 0;
470
471	u64 *base;
472	u64 *size;
473	u64 mc_memory_base = 0;
474	u64 mc_memory_size = 0;
475	u16 total_memory_banks;
476
477	ft_cpu_setup(blob, bd);
478
479	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
480
481	if (mc_memory_base != 0)
482		mc_memory_bank++;
483
484	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
485
486	base = calloc(total_memory_banks, sizeof(u64));
487	size = calloc(total_memory_banks, sizeof(u64));
488
489	/* fixup DT for the two GPP DDR banks */
490	base[0] = gd->bd->bi_dram[0].start;
491	size[0] = gd->bd->bi_dram[0].size;
492	base[1] = gd->bd->bi_dram[1].start;
493	size[1] = gd->bd->bi_dram[1].size;
494
495#ifdef CONFIG_RESV_RAM
496	/* reduce size if reserved memory is within this bank */
497	if (gd->arch.resv_ram >= base[0] &&
498	    gd->arch.resv_ram < base[0] + size[0])
499		size[0] = gd->arch.resv_ram - base[0];
500	else if (gd->arch.resv_ram >= base[1] &&
501		 gd->arch.resv_ram < base[1] + size[1])
502		size[1] = gd->arch.resv_ram - base[1];
503#endif
504
505	if (mc_memory_base != 0) {
506		for (i = 0; i <= total_memory_banks; i++) {
507			if (base[i] == 0 && size[i] == 0) {
508				base[i] = mc_memory_base;
509				size[i] = mc_memory_size;
510				break;
511			}
512		}
513	}
514
515	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
516
517	fdt_fsl_mc_fixup_iommu_map_entry(blob);
518
519	fsl_fdt_fixup_dr_usb(blob, bd);
520
521	fsl_fdt_fixup_flash(blob);
522
523#ifdef CONFIG_FSL_MC_ENET
524	fdt_fixup_board_enet(blob);
525	fdt_reserve_mc_mem(blob, 0x300);
526#endif
527
528	fdt_fixup_icid(blob);
529
530	return 0;
531}
532#endif
533
534void qixis_dump_switch(void)
535{
536#ifdef CONFIG_FSL_QIXIS
537	int i, nr_of_cfgsw;
538
539	QIXIS_WRITE(cms[0], 0x00);
540	nr_of_cfgsw = QIXIS_READ(cms[1]);
541
542	puts("DIP switch settings dump:\n");
543	for (i = 1; i <= nr_of_cfgsw; i++) {
544		QIXIS_WRITE(cms[0], i);
545		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
546	}
547#endif
548}
549
550/*
551 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
552 * Both slots has 0x54, resulting 2nd slot unusable.
553 */
554void update_spd_address(unsigned int ctrl_num,
555			unsigned int slot,
556			unsigned int *addr)
557{
558#ifndef CONFIG_TARGET_LS2081ARDB
559#ifdef CONFIG_FSL_QIXIS
560	u8 sw;
561
562	sw = QIXIS_READ(arch);
563	if ((sw & 0xf) < 0x3) {
564		if (ctrl_num == 1 && slot == 0)
565			*addr = SPD_EEPROM_ADDRESS4;
566		else if (ctrl_num == 1 && slot == 1)
567			*addr = SPD_EEPROM_ADDRESS3;
568	}
569#endif
570#endif
571}
572