1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2019-2021 NXP
5 */
6
7#include <common.h>
8#include <clock_legacy.h>
9#include <i2c.h>
10#include <fdt_support.h>
11#include <fsl_ddr_sdram.h>
12#include <init.h>
13#include <asm/global_data.h>
14#include <asm/io.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/fsl_serdes.h>
17#include <asm/arch/fdt.h>
18#include <asm/arch/mmu.h>
19#include <asm/arch/cpu.h>
20#include <asm/arch/soc.h>
21#include <asm/arch-fsl-layerscape/fsl_icid.h>
22#include <ahci.h>
23#include <hwconfig.h>
24#include <mmc.h>
25#include <scsi.h>
26#include <fm_eth.h>
27#include <fsl_csu.h>
28#include <fsl_esdhc.h>
29#include <fsl_ifc.h>
30#include <spl.h>
31#include "../common/i2c_mux.h"
32
33#include "../common/vid.h"
34#include "../common/qixis.h"
35#include "ls1046aqds_qixis.h"
36
37DECLARE_GLOBAL_DATA_PTR;
38
39#ifdef CONFIG_TFABOOT
40struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
41	{
42		"nor0",
43		CFG_SYS_NOR0_CSPR,
44		CFG_SYS_NOR0_CSPR_EXT,
45		CFG_SYS_NOR_AMASK,
46		CFG_SYS_NOR_CSOR,
47		{
48			CFG_SYS_NOR_FTIM0,
49			CFG_SYS_NOR_FTIM1,
50			CFG_SYS_NOR_FTIM2,
51			CFG_SYS_NOR_FTIM3
52		},
53
54	},
55	{
56		"nor1",
57		CFG_SYS_NOR1_CSPR,
58		CFG_SYS_NOR1_CSPR_EXT,
59		CFG_SYS_NOR_AMASK,
60		CFG_SYS_NOR_CSOR,
61		{
62			CFG_SYS_NOR_FTIM0,
63			CFG_SYS_NOR_FTIM1,
64			CFG_SYS_NOR_FTIM2,
65			CFG_SYS_NOR_FTIM3
66		},
67	},
68	{
69		"nand",
70		CFG_SYS_NAND_CSPR,
71		CFG_SYS_NAND_CSPR_EXT,
72		CFG_SYS_NAND_AMASK,
73		CFG_SYS_NAND_CSOR,
74		{
75			CFG_SYS_NAND_FTIM0,
76			CFG_SYS_NAND_FTIM1,
77			CFG_SYS_NAND_FTIM2,
78			CFG_SYS_NAND_FTIM3
79		},
80	},
81	{
82		"fpga",
83		CFG_SYS_FPGA_CSPR,
84		CFG_SYS_FPGA_CSPR_EXT,
85		CFG_SYS_FPGA_AMASK,
86		CFG_SYS_FPGA_CSOR,
87		{
88			CFG_SYS_FPGA_FTIM0,
89			CFG_SYS_FPGA_FTIM1,
90			CFG_SYS_FPGA_FTIM2,
91			CFG_SYS_FPGA_FTIM3
92		},
93	}
94};
95
96struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
97	{
98		"nand",
99		CFG_SYS_NAND_CSPR,
100		CFG_SYS_NAND_CSPR_EXT,
101		CFG_SYS_NAND_AMASK,
102		CFG_SYS_NAND_CSOR,
103		{
104			CFG_SYS_NAND_FTIM0,
105			CFG_SYS_NAND_FTIM1,
106			CFG_SYS_NAND_FTIM2,
107			CFG_SYS_NAND_FTIM3
108		},
109	},
110	{
111		"nor0",
112		CFG_SYS_NOR0_CSPR,
113		CFG_SYS_NOR0_CSPR_EXT,
114		CFG_SYS_NOR_AMASK,
115		CFG_SYS_NOR_CSOR,
116		{
117			CFG_SYS_NOR_FTIM0,
118			CFG_SYS_NOR_FTIM1,
119			CFG_SYS_NOR_FTIM2,
120			CFG_SYS_NOR_FTIM3
121		},
122	},
123	{
124		"nor1",
125		CFG_SYS_NOR1_CSPR,
126		CFG_SYS_NOR1_CSPR_EXT,
127		CFG_SYS_NOR_AMASK,
128		CFG_SYS_NOR_CSOR,
129		{
130			CFG_SYS_NOR_FTIM0,
131			CFG_SYS_NOR_FTIM1,
132			CFG_SYS_NOR_FTIM2,
133			CFG_SYS_NOR_FTIM3
134		},
135	},
136	{
137		"fpga",
138		CFG_SYS_FPGA_CSPR,
139		CFG_SYS_FPGA_CSPR_EXT,
140		CFG_SYS_FPGA_AMASK,
141		CFG_SYS_FPGA_CSOR,
142		{
143			CFG_SYS_FPGA_FTIM0,
144			CFG_SYS_FPGA_FTIM1,
145			CFG_SYS_FPGA_FTIM2,
146			CFG_SYS_FPGA_FTIM3
147		},
148	}
149};
150
151void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
152{
153	enum boot_src src = get_boot_src();
154
155	if (src == BOOT_SOURCE_IFC_NAND)
156		regs_info->regs = ifc_cfg_nand_boot;
157	else
158		regs_info->regs = ifc_cfg_nor_boot;
159	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
160}
161
162#endif
163
164enum {
165	MUX_TYPE_GPIO,
166};
167
168int checkboard(void)
169{
170#ifdef CONFIG_TFABOOT
171	enum boot_src src = get_boot_src();
172#endif
173	char buf[64];
174#ifndef CONFIG_SD_BOOT
175	u8 sw;
176#endif
177
178	puts("Board: LS1046AQDS, boot from ");
179
180#ifdef CONFIG_TFABOOT
181	if (src == BOOT_SOURCE_SD_MMC)
182		puts("SD\n");
183	else {
184#endif
185
186#ifdef CONFIG_SD_BOOT
187	puts("SD\n");
188#else
189	sw = QIXIS_READ(brdcfg[0]);
190	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
191
192	if (sw < 0x8)
193		printf("vBank: %d\n", sw);
194	else if (sw == 0x8)
195		puts("PromJet\n");
196	else if (sw == 0x9)
197		puts("NAND\n");
198	else if (sw == 0xF)
199		printf("QSPI\n");
200	else
201		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
202#endif
203
204#ifdef CONFIG_TFABOOT
205	}
206#endif
207	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
208	       QIXIS_READ(id), QIXIS_READ(arch));
209
210	printf("FPGA:  v%d (%s), build %d\n",
211	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
212	       (int)qixis_read_minor());
213
214	return 0;
215}
216
217bool if_board_diff_clk(void)
218{
219	u8 diff_conf = QIXIS_READ(brdcfg[11]);
220
221	return diff_conf & 0x40;
222}
223
224unsigned long get_board_sys_clk(void)
225{
226	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
227
228	switch (sysclk_conf & 0x0f) {
229	case QIXIS_SYSCLK_64:
230		return 64000000;
231	case QIXIS_SYSCLK_83:
232		return 83333333;
233	case QIXIS_SYSCLK_100:
234		return 100000000;
235	case QIXIS_SYSCLK_125:
236		return 125000000;
237	case QIXIS_SYSCLK_133:
238		return 133333333;
239	case QIXIS_SYSCLK_150:
240		return 150000000;
241	case QIXIS_SYSCLK_160:
242		return 160000000;
243	case QIXIS_SYSCLK_166:
244		return 166666666;
245	}
246
247	return 66666666;
248}
249
250unsigned long get_board_ddr_clk(void)
251{
252	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
253
254	if (if_board_diff_clk())
255		return get_board_sys_clk();
256	switch ((ddrclk_conf & 0x30) >> 4) {
257	case QIXIS_DDRCLK_100:
258		return 100000000;
259	case QIXIS_DDRCLK_125:
260		return 125000000;
261	case QIXIS_DDRCLK_133:
262		return 133333333;
263	}
264
265	return 66666666;
266}
267
268#ifdef CONFIG_LPUART
269u32 get_lpuart_clk(void)
270{
271	return gd->bus_clk;
272}
273#endif
274
275int dram_init(void)
276{
277	/*
278	 * When resuming from deep sleep, the I2C channel may not be
279	 * in the default channel. So, switch to the default channel
280	 * before accessing DDR SPD.
281	 *
282	 * PCA9547 mount on I2C1 bus
283	 */
284	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
285	fsl_initdram();
286#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
287	defined(CONFIG_SPL_BUILD)
288	/* This will break-before-make MMU for DDR */
289	update_early_mmu_table();
290#endif
291
292	return 0;
293}
294
295int i2c_multiplexer_select_vid_channel(u8 channel)
296{
297	return select_i2c_ch_pca9547(channel, 0);
298}
299
300int board_early_init_f(void)
301{
302	u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
303#ifdef CONFIG_HAS_FSL_XHCI_USB
304	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
305	u32 usb_pwrfault;
306#endif
307#ifdef CONFIG_LPUART
308	u8 uart;
309#endif
310
311	/*
312	 * Enable secure system counter for timer
313	 */
314	out_le32(cntcr, 0x1);
315
316#if defined(CONFIG_SYS_I2C_EARLY_INIT)
317	i2c_early_init_f();
318#endif
319	fsl_lsch2_early_init_f();
320
321#ifdef CONFIG_HAS_FSL_XHCI_USB
322	out_be32(&scfg->rcwpmuxcr0, 0x3333);
323	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
324	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
325			SCFG_USBPWRFAULT_USB3_SHIFT) |
326			(SCFG_USBPWRFAULT_DEDICATED <<
327			SCFG_USBPWRFAULT_USB2_SHIFT) |
328			(SCFG_USBPWRFAULT_SHARED <<
329			SCFG_USBPWRFAULT_USB1_SHIFT);
330	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
331#endif
332
333#ifdef CONFIG_LPUART
334	/* We use lpuart0 as system console */
335	uart = QIXIS_READ(brdcfg[14]);
336	uart &= ~CFG_UART_MUX_MASK;
337	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
338	QIXIS_WRITE(brdcfg[14], uart);
339#endif
340
341	return 0;
342}
343
344#ifdef CONFIG_FSL_DEEP_SLEEP
345/* determine if it is a warm boot */
346bool is_warm_boot(void)
347{
348#define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
349	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
350
351	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
352		return 1;
353
354	return 0;
355}
356#endif
357
358int config_board_mux(int ctrl_type)
359{
360	u8 reg14;
361
362	reg14 = QIXIS_READ(brdcfg[14]);
363
364	switch (ctrl_type) {
365	case MUX_TYPE_GPIO:
366		reg14 = (reg14 & (~0x6)) | 0x2;
367		break;
368	default:
369		puts("Unsupported mux interface type\n");
370		return -1;
371	}
372
373	QIXIS_WRITE(brdcfg[14], reg14);
374
375	return 0;
376}
377
378int config_serdes_mux(void)
379{
380	return 0;
381}
382
383#ifdef CONFIG_MISC_INIT_R
384int misc_init_r(void)
385{
386	if (hwconfig("gpio"))
387		config_board_mux(MUX_TYPE_GPIO);
388
389	return 0;
390}
391#endif
392
393int board_init(void)
394{
395	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
396
397#ifdef CFG_SYS_FSL_SERDES
398	config_serdes_mux();
399#endif
400
401	if (adjust_vdd(0))
402		printf("Warning: Adjusting core voltage failed.\n");
403
404#ifdef CONFIG_NXP_ESBC
405	/*
406	 * In case of Secure Boot, the IBR configures the SMMU
407	 * to allow only Secure transactions.
408	 * SMMU must be reset in bypass mode.
409	 * Set the ClientPD bit and Clear the USFCFG Bit
410	 */
411	u32 val;
412	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
413	out_le32(SMMU_SCR0, val);
414	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
415	out_le32(SMMU_NSCR0, val);
416#endif
417
418	return 0;
419}
420
421#ifdef CONFIG_OF_BOARD_SETUP
422int ft_board_setup(void *blob, struct bd_info *bd)
423{
424	u64 base[CONFIG_NR_DRAM_BANKS];
425	u64 size[CONFIG_NR_DRAM_BANKS];
426	u8 reg;
427
428	/* fixup DT for the two DDR banks */
429	base[0] = gd->bd->bi_dram[0].start;
430	size[0] = gd->bd->bi_dram[0].size;
431	base[1] = gd->bd->bi_dram[1].start;
432	size[1] = gd->bd->bi_dram[1].size;
433
434	fdt_fixup_memory_banks(blob, base, size, 2);
435	ft_cpu_setup(blob, bd);
436
437#ifdef CONFIG_FMAN_ENET
438	fdt_fixup_board_enet(blob);
439#endif
440
441	fdt_fixup_icid(blob);
442
443	reg = QIXIS_READ(brdcfg[0]);
444	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
445
446	/* Disable IFC if QSPI is enabled */
447	if (reg == 0xF)
448		do_fixup_by_compat(blob, "fsl,ifc",
449				   "status", "disabled", 8 + 1, 1);
450
451	return 0;
452}
453#endif
454
455u8 flash_read8(void *addr)
456{
457	return __raw_readb(addr + 1);
458}
459
460void flash_write16(u16 val, void *addr)
461{
462	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
463
464	__raw_writew(shftval, addr);
465}
466
467u16 flash_read16(void *addr)
468{
469	u16 val = __raw_readw(addr);
470
471	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
472}
473
474#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
475void *env_sf_get_env_addr(void)
476{
477	return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
478}
479#endif
480