1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019-2022 NXP
4 */
5
6#include <common.h>
7#include <display_options.h>
8#include <init.h>
9#include <malloc.h>
10#include <errno.h>
11#include <fsl_ddr.h>
12#include <net.h>
13#include <asm/global_data.h>
14#include <asm/io.h>
15#include <hwconfig.h>
16#include <fdt_support.h>
17#include <linux/libfdt.h>
18#include <env_internal.h>
19#include <asm/arch-fsl-layerscape/soc.h>
20#include <asm/arch-fsl-layerscape/fsl_icid.h>
21#include <i2c.h>
22#include <asm/arch/soc.h>
23#include <fsl_immap.h>
24#include <netdev.h>
25
26#include <fdtdec.h>
27#include <miiphy.h>
28#include "../common/qixis.h"
29#include "../drivers/net/fsl_enetc.h"
30
31DECLARE_GLOBAL_DATA_PTR;
32
33int config_board_mux(void)
34{
35#ifndef CONFIG_LPUART
36#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
37	u8 reg;
38
39	reg = QIXIS_READ(brdcfg[13]);
40	/* Field| Function
41	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
42	 * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
43	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
44	 * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
45	 */
46	reg &= ~(0xf0);
47	reg |= 0xb0;
48	QIXIS_WRITE(brdcfg[13], reg);
49
50	reg = QIXIS_READ(brdcfg[15]);
51	/* Field| Function
52	 * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
53	 * CAN1 | 0= CAN #1 transceiver enabled
54	 * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
55	 * CAN2 | 0= CAN #2 transceiver enabled
56	 */
57	reg &= ~(0xc0);
58	QIXIS_WRITE(brdcfg[15], reg);
59#endif
60#endif
61
62	return 0;
63}
64
65#ifdef CONFIG_LPUART
66u32 get_lpuart_clk(void)
67{
68	return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
69}
70#endif
71
72int board_init(void)
73{
74#ifndef CONFIG_SYS_EARLY_PCI_INIT
75	pci_init();
76#endif
77
78#if defined(CONFIG_TARGET_LS1028ARDB)
79	u8 val = I2C_MUX_CH_DEFAULT;
80
81#if !CONFIG_IS_ENABLED(DM_I2C)
82	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
83#else
84	struct udevice *dev;
85
86	if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
87		dm_i2c_write(dev, 0x0b, &val, 1);
88#endif
89#endif
90
91#if defined(CONFIG_TARGET_LS1028ARDB)
92	u8 reg;
93
94	reg = QIXIS_READ(brdcfg[4]);
95	/*
96	 * Field | Function
97	 * 3     | DisplayPort Power Enable (net DP_PWR_EN):
98	 * DPPWR | 0= DP_PWR is enabled.
99	 */
100	reg &= ~(DP_PWD_EN_DEFAULT_MASK);
101	QIXIS_WRITE(brdcfg[4], reg);
102#endif
103	return 0;
104}
105
106int board_eth_init(struct bd_info *bis)
107{
108	return pci_eth_init(bis);
109}
110
111#ifdef CONFIG_MISC_INIT_R
112int misc_init_r(void)
113{
114	config_board_mux();
115
116	return 0;
117}
118#endif
119
120int board_early_init_f(void)
121{
122#ifdef CONFIG_LPUART
123	u8 uart;
124#endif
125
126#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
127	i2c_early_init_f();
128#endif
129
130	fsl_lsch3_early_init_f();
131
132#ifdef CONFIG_LPUART
133	/*
134	 * Field| Function
135	 * --------------------------------------------------------------
136	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
137	 * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
138	 * --------------------------------------------------------------
139	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
140	 * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
141	 */
142	/* use lpuart0 as system console */
143	uart = QIXIS_READ(brdcfg[13]);
144	uart &= ~CFG_LPUART_MUX_MASK;
145	uart |= CFG_LPUART_EN;
146	QIXIS_WRITE(brdcfg[13], uart);
147#endif
148
149	return 0;
150}
151
152void detail_board_ddr_info(void)
153{
154	puts("\nDDR    ");
155	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
156	print_ddr_info(0);
157}
158
159int esdhc_status_fixup(void *blob, const char *compat)
160{
161	void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
162	char esdhc1_path[] = "/soc/mmc@2140000";
163	char esdhc2_path[] = "/soc/mmc@2150000";
164	char dspi1_path[] = "/soc/spi@2100000";
165	char dspi2_path[] = "/soc/spi@2110000";
166	u32 mux_sdhc1, mux_sdhc2;
167	u32 io = 0;
168
169	/*
170	 * The PMUX IO-expander for mux select is used to control
171	 * the muxing of various onboard interfaces.
172	 */
173
174	io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
175	mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
176
177	/* Disable esdhc1/dspi1 if not selected. */
178	if (mux_sdhc1 != 0)
179		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
180				 sizeof("disabled"), 1);
181	if (mux_sdhc1 != 2)
182		do_fixup_by_path(blob, dspi1_path, "status", "disabled",
183				 sizeof("disabled"), 1);
184
185	io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
186	mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
187
188	/* Disable esdhc2/dspi2 if not selected. */
189	if (mux_sdhc2 != 0)
190		do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
191				 sizeof("disabled"), 1);
192	if (mux_sdhc2 != 2)
193		do_fixup_by_path(blob, dspi2_path, "status", "disabled",
194				 sizeof("disabled"), 1);
195
196	return 0;
197}
198
199#ifdef CONFIG_OF_BOARD_SETUP
200int ft_board_setup(void *blob, struct bd_info *bd)
201{
202	u64 base[CONFIG_NR_DRAM_BANKS];
203	u64 size[CONFIG_NR_DRAM_BANKS];
204
205	ft_cpu_setup(blob, bd);
206
207	/* fixup DT for the two GPP DDR banks */
208	base[0] = gd->bd->bi_dram[0].start;
209	size[0] = gd->bd->bi_dram[0].size;
210	base[1] = gd->bd->bi_dram[1].start;
211	size[1] = gd->bd->bi_dram[1].size;
212
213#ifdef CONFIG_RESV_RAM
214	/* reduce size if reserved memory is within this bank */
215	if (gd->arch.resv_ram >= base[0] &&
216	    gd->arch.resv_ram < base[0] + size[0])
217		size[0] = gd->arch.resv_ram - base[0];
218	else if (gd->arch.resv_ram >= base[1] &&
219		 gd->arch.resv_ram < base[1] + size[1])
220		size[1] = gd->arch.resv_ram - base[1];
221#endif
222
223	fdt_fixup_memory_banks(blob, base, size, 2);
224
225	fdt_fixup_icid(blob);
226
227#ifdef CONFIG_FSL_ENETC
228	fdt_fixup_enetc_mac(blob);
229#endif
230
231	return 0;
232}
233#endif
234
235#ifdef CONFIG_FSL_QIXIS
236int checkboard(void)
237{
238#ifdef CONFIG_TFABOOT
239	enum boot_src src = get_boot_src();
240#endif
241	u8 sw;
242
243	int clock;
244	char *board;
245	char buf[64] = {0};
246	static const char *freq[6] = {"100.00", "125.00", "156.25",
247					"161.13", "322.26", "100.00 SS"};
248
249	cpu_name(buf);
250	/* find the board details */
251	sw = QIXIS_READ(id);
252
253	switch (sw) {
254	case 0x46:
255		board = "QDS";
256		break;
257	case 0x47:
258		board = "RDB";
259		break;
260	case 0x49:
261		board = "HSSI";
262		break;
263	default:
264		board = "unknown";
265		break;
266	}
267
268	sw = QIXIS_READ(arch);
269	printf("Board: %s-%s, Version: %c, boot from ",
270	       buf, board, (sw & 0xf) + 'A' - 1);
271
272	sw = QIXIS_READ(brdcfg[0]);
273	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
274
275#ifdef CONFIG_TFABOOT
276	if (src == BOOT_SOURCE_SD_MMC) {
277		puts("SD\n");
278	} else if (src == BOOT_SOURCE_SD_MMC2) {
279		puts("eMMC\n");
280	} else {
281#endif
282#ifdef CONFIG_SD_BOOT
283		puts("SD\n");
284#elif defined(CONFIG_EMMC_BOOT)
285		puts("eMMC\n");
286#else
287		switch (sw) {
288		case 0:
289		case 4:
290			printf("NOR\n");
291			break;
292		case 1:
293			printf("NAND\n");
294			break;
295		default:
296			printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
297			break;
298		}
299#endif
300#ifdef CONFIG_TFABOOT
301	}
302#endif
303
304	printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
305	puts("SERDES1 Reference : ");
306
307	sw = QIXIS_READ(brdcfg[2]);
308#ifdef CONFIG_TARGET_LS1028ARDB
309	clock = (sw >> 6) & 3;
310#else
311	clock = (sw >> 4) & 0xf;
312#endif
313
314	printf("Clock1 = %sMHz ", freq[clock]);
315#ifdef CONFIG_TARGET_LS1028ARDB
316	clock = (sw >> 4) & 3;
317#else
318	clock = sw & 0xf;
319#endif
320	printf("Clock2 = %sMHz\n", freq[clock]);
321
322	return 0;
323}
324#endif
325
326void *video_hw_init(void)
327{
328	return NULL;
329}
330