1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Amarula Solutions B.V. 4 * Copyright (C) 2016 Engicam S.r.l. 5 * Author: Jagan Teki <jagan@amarulasolutions.com> 6 */ 7 8#include <common.h> 9 10#include <asm/io.h> 11#include <asm/gpio.h> 12#include <linux/sizes.h> 13 14#include <asm/arch/clock.h> 15#include <asm/arch/crm_regs.h> 16#include <asm/arch/iomux.h> 17#include <asm/arch/mx6-pins.h> 18#include <asm/arch/sys_proto.h> 19#include <asm/mach-imx/iomux-v3.h> 20#include <asm/mach-imx/video.h> 21 22#include "../common/board.h" 23 24#ifdef CONFIG_NAND_MXS 25#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) 26#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ 27 PAD_CTL_SRE_FAST) 28#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) 29 30static iomux_v3_cfg_t gpmi_pads[] = { 31 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 32 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 33 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 34 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), 35 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 36 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 37 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 38 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 39 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 40 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 41 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 42 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 43 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 44 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 45 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 46}; 47 48void setup_gpmi_nand(void) 49{ 50 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 51 52 /* config gpmi nand iomux */ 53 SETUP_IOMUX_PADS(gpmi_pads); 54 55 /* gate ENFC_CLK_ROOT clock first,before clk source switch */ 56 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 57 58 /* config gpmi and bch clock to 100 MHz */ 59 clrsetbits_le32(&mxc_ccm->cs2cdr, 60 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 61 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 62 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 63 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 64 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 65 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 66 67 /* enable ENFC_CLK_ROOT clock */ 68 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 69 70 /* enable gpmi and bch clock gating */ 71 setbits_le32(&mxc_ccm->CCGR4, 72 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 73 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 74 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 76 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 77 78 /* enable apbh clock gating */ 79 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 80} 81#endif 82 83#if defined(CONFIG_VIDEO_IPUV3) 84static iomux_v3_cfg_t const rgb_pads[] = { 85 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), 86 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), 87 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), 88 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), 89 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), 90 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), 91 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), 92 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), 93 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), 94 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), 95 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), 96 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), 97 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), 98 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), 99 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), 100 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), 101 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), 102 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), 103 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), 104 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), 105 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), 106 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), 107}; 108 109static void enable_rgb(struct display_info_t const *dev) 110{ 111 SETUP_IOMUX_PADS(rgb_pads); 112} 113 114struct display_info_t const displays[] = { 115 { 116 .bus = -1, 117 .addr = 0, 118 .pixfmt = IPU_PIX_FMT_RGB666, 119 .detect = NULL, 120 .enable = enable_rgb, 121 .mode = { 122 .name = "Amp-WD", 123 .refresh = 60, 124 .xres = 800, 125 .yres = 480, 126 .pixclock = 30000, 127 .left_margin = 30, 128 .right_margin = 30, 129 .upper_margin = 5, 130 .lower_margin = 5, 131 .hsync_len = 64, 132 .vsync_len = 20, 133 .sync = FB_SYNC_EXT, 134 .vmode = FB_VMODE_NONINTERLACED 135 } 136 }, 137}; 138 139size_t display_count = ARRAY_SIZE(displays); 140 141void setup_display(void) 142{ 143 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 144 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 145 int reg; 146 147 enable_ipu_clock(); 148 149 /* Turn on LDB0,IPU,IPU DI0 clocks */ 150 reg = __raw_readl(&mxc_ccm->CCGR3); 151 reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); 152 writel(reg, &mxc_ccm->CCGR3); 153 154 /* set LDB0, LDB1 clk select to 011/011 */ 155 reg = readl(&mxc_ccm->cs2cdr); 156 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | 157 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 158 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | 159 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 160 writel(reg, &mxc_ccm->cs2cdr); 161 162 reg = readl(&mxc_ccm->cscmr2); 163 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 164 writel(reg, &mxc_ccm->cscmr2); 165 166 reg = readl(&mxc_ccm->chsccdr); 167 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << 168 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 169 writel(reg, &mxc_ccm->chsccdr); 170 171 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | 172 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | 173 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | 174 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | 175 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | 176 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | 177 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 178 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | 179 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 180 writel(reg, &iomux->gpr[2]); 181 182 reg = readl(&iomux->gpr[3]); 183 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | 184 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << 185 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 186 writel(reg, &iomux->gpr[3]); 187} 188#endif /* CONFIG_VIDEO_IPUV3 */ 189 190#ifdef CONFIG_ENV_IS_IN_MMC 191int board_mmc_get_env_dev(int devno) 192{ 193 /* i.CoreM6 RQS has USDHC3 for SD and USDHC4 for eMMC */ 194 return (devno == 0) ? 0: (devno - 1); 195} 196#endif 197