1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2017 Tuomas Tynkkynen
4 */
5
6#include <common.h>
7#include <cpu_func.h>
8#include <dm.h>
9#include <efi.h>
10#include <efi_loader.h>
11#include <fdtdec.h>
12#include <init.h>
13#include <log.h>
14#include <usb.h>
15#include <virtio_types.h>
16#include <virtio.h>
17
18#include <linux/kernel.h>
19#include <linux/sizes.h>
20
21/* GUIDs for capsule updatable firmware images */
22#define QEMU_ARM_UBOOT_IMAGE_GUID \
23	EFI_GUID(0xf885b085, 0x99f8, 0x45af, 0x84, 0x7d, \
24		 0xd5, 0x14, 0x10, 0x7a, 0x4a, 0x2c)
25
26#define QEMU_ARM64_UBOOT_IMAGE_GUID \
27	EFI_GUID(0x058b7d83, 0x50d5, 0x4c47, 0xa1, 0x95, \
28		 0x60, 0xd8, 0x6a, 0xd3, 0x41, 0xc4)
29
30#ifdef CONFIG_ARM64
31#include <asm/armv8/mmu.h>
32
33#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
34struct efi_fw_image fw_images[] = {
35#if defined(CONFIG_TARGET_QEMU_ARM_32BIT)
36	{
37		.image_type_id = QEMU_ARM_UBOOT_IMAGE_GUID,
38		.fw_name = u"Qemu-Arm-UBOOT",
39		.image_index = 1,
40	},
41#elif defined(CONFIG_TARGET_QEMU_ARM_64BIT)
42	{
43		.image_type_id = QEMU_ARM64_UBOOT_IMAGE_GUID,
44		.fw_name = u"Qemu-Arm-UBOOT",
45		.image_index = 1,
46	},
47#endif
48};
49
50struct efi_capsule_update_info update_info = {
51	.num_images = ARRAY_SIZE(fw_images)
52	.images = fw_images,
53};
54
55#endif /* EFI_HAVE_CAPSULE_SUPPORT */
56
57static struct mm_region qemu_arm64_mem_map[] = {
58	{
59		/* Flash */
60		.virt = 0x00000000UL,
61		.phys = 0x00000000UL,
62		.size = 0x08000000UL,
63		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
64			 PTE_BLOCK_INNER_SHARE
65	}, {
66		/* Lowmem peripherals */
67		.virt = 0x08000000UL,
68		.phys = 0x08000000UL,
69		.size = 0x38000000,
70		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
71			 PTE_BLOCK_NON_SHARE |
72			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
73	}, {
74		/* RAM */
75		.virt = 0x40000000UL,
76		.phys = 0x40000000UL,
77		.size = 255UL * SZ_1G,
78		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
79			 PTE_BLOCK_INNER_SHARE
80	}, {
81		/* Highmem PCI-E ECAM memory area */
82		.virt = 0x4010000000ULL,
83		.phys = 0x4010000000ULL,
84		.size = 0x10000000,
85		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
86			 PTE_BLOCK_NON_SHARE |
87			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
88	}, {
89		/* Highmem PCI-E MMIO memory area */
90		.virt = 0x8000000000ULL,
91		.phys = 0x8000000000ULL,
92		.size = 0x8000000000ULL,
93		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
94			 PTE_BLOCK_NON_SHARE |
95			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
96	}, {
97		/* List terminator */
98		0,
99	}
100};
101
102struct mm_region *mem_map = qemu_arm64_mem_map;
103#endif
104
105int board_init(void)
106{
107	return 0;
108}
109
110int board_late_init(void)
111{
112	/*
113	 * Make sure virtio bus is enumerated so that peripherals
114	 * on the virtio bus can be discovered by their drivers
115	 */
116	virtio_init();
117
118	/* start usb so that usb keyboard can be used as input device */
119	if (CONFIG_IS_ENABLED(USB_KEYBOARD))
120		usb_init();
121
122	return 0;
123}
124
125int dram_init(void)
126{
127	if (fdtdec_setup_mem_size_base() != 0)
128		return -EINVAL;
129
130	/*
131	 * When LPAE is enabled (ARMv7),
132	 * 1:1 mapping is created using 2 MB blocks.
133	 *
134	 * In case amount of memory provided to QEMU
135	 * is not multiple of 2 MB, round down the amount
136	 * of available memory to avoid hang during MMU
137	 * initialization.
138	 */
139	if (CONFIG_IS_ENABLED(ARMV7_LPAE))
140		gd->ram_size -= (gd->ram_size % 0x200000);
141
142	return 0;
143}
144
145int dram_init_banksize(void)
146{
147	fdtdec_setup_memory_banksize();
148
149	return 0;
150}
151
152void *board_fdt_blob_setup(int *err)
153{
154	*err = 0;
155	/* QEMU loads a generated DTB for us at the start of RAM. */
156	return (void *)CFG_SYS_SDRAM_BASE;
157}
158
159void enable_caches(void)
160{
161	 icache_enable();
162	 dcache_enable();
163}
164
165#ifdef CONFIG_ARM64
166#define __W	"w"
167#else
168#define __W
169#endif
170
171u8 flash_read8(void *addr)
172{
173	u8 ret;
174
175	asm("ldrb %" __W "0, %1" : "=r"(ret) : "m"(*(u8 *)addr));
176	return ret;
177}
178
179u16 flash_read16(void *addr)
180{
181	u16 ret;
182
183	asm("ldrh %" __W "0, %1" : "=r"(ret) : "m"(*(u16 *)addr));
184	return ret;
185}
186
187u32 flash_read32(void *addr)
188{
189	u32 ret;
190
191	asm("ldr %" __W "0, %1" : "=r"(ret) : "m"(*(u32 *)addr));
192	return ret;
193}
194
195void flash_write8(u8 value, void *addr)
196{
197	asm("strb %" __W "1, %0" : "=m"(*(u8 *)addr) : "r"(value));
198}
199
200void flash_write16(u16 value, void *addr)
201{
202	asm("strh %" __W "1, %0" : "=m"(*(u16 *)addr) : "r"(value));
203}
204
205void flash_write32(u32 value, void *addr)
206{
207	asm("str %" __W "1, %0" : "=m"(*(u32 *)addr) : "r"(value));
208}
209