1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2011
4 * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
5 *
6 * Based on Kirkwood support:
7 * (C) Copyright 2009
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 */
11
12#include <common.h>
13#include <init.h>
14#include <log.h>
15#include <miiphy.h>
16#include <net.h>
17#include <netdev.h>
18#include <asm/arch/cpu.h>
19#include <asm/arch/soc.h>
20#include <asm/arch/mpp.h>
21#include <asm/arch/gpio.h>
22#include <asm/global_data.h>
23#include "dns325.h"
24
25DECLARE_GLOBAL_DATA_PTR;
26
27int board_early_init_f(void)
28{
29	/* Gpio configuration */
30	mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
31			  DNS325_OE_LOW, DNS325_OE_HIGH);
32
33	/* Multi-Purpose Pins Functionality configuration */
34	static const u32 kwmpp_config[] = {
35		MPP0_NF_IO2,
36		MPP1_NF_IO3,
37		MPP2_NF_IO4,
38		MPP3_NF_IO5,
39		MPP4_NF_IO6,
40		MPP5_NF_IO7,
41		MPP6_SYSRST_OUTn,
42		MPP7_GPO,
43		MPP8_TW_SDA,
44		MPP9_TW_SCK,
45		MPP10_UART0_TXD,
46		MPP11_UART0_RXD,
47		MPP12_SD_CLK,
48		MPP13_SD_CMD,
49		MPP14_SD_D0,
50		MPP15_SD_D1,
51		MPP16_SD_D2,
52		MPP17_SD_D3,
53		MPP18_NF_IO0,
54		MPP19_NF_IO1,
55		MPP20_SATA1_ACTn,	/* sata1(left) status led */
56		MPP21_SATA0_ACTn,	/* sata0(right) status led */
57		MPP22_GPIO,
58		MPP23_GPIO,
59		MPP24_GPIO,		/* power off out */
60		MPP25_GPIO,
61		MPP26_GPIO,		/* power led */
62		MPP27_GPIO,		/* sata0(right) error led */
63		MPP28_GPIO,		/* sata1(left) error led */
64		MPP29_GPIO,		/* usb error led */
65		MPP30_GPIO,
66		MPP31_GPIO,
67		MPP32_GPIO,
68		MPP33_GPIO,
69		MPP34_GPIO,		/* power key */
70		MPP35_GPIO,
71		MPP36_GPIO,
72		MPP37_GPIO,
73		MPP38_GPIO,
74		MPP39_GPIO,		/* enable sata 0 */
75		MPP40_GPIO,		/* enable sata 1 */
76		MPP41_GPIO,		/* hdd0 present */
77		MPP42_GPIO,		/* hdd1 present */
78		MPP43_GPIO,		/* usb status led */
79		MPP44_GPIO,		/* fan status */
80		MPP45_GPIO,		/* fan high speed */
81		MPP46_GPIO,		/* fan low speed */
82		MPP47_GPIO,		/* usb umount */
83		MPP48_GPIO,		/* factory reset */
84		MPP49_GPIO,		/* thermal sensor */
85		0
86	};
87	kirkwood_mpp_conf(kwmpp_config, NULL);
88
89	kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
90
91	kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
92	kw_gpio_set_value(DNS325_GPIO_SATA1_EN , 1);
93	return 0;
94}
95
96int board_init(void)
97{
98	/* Boot parameters address */
99	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
100
101	return 0;
102}
103
104#ifdef CONFIG_RESET_PHY_R
105/* Configure and initialize PHY */
106void reset_phy(void)
107{
108	u16 reg;
109	u16 devadr;
110	char *name = "egiga0";
111
112	if (miiphy_set_current_dev(name))
113		return;
114
115	/* command to read PHY dev address */
116	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
117		printf("Err..(%s) could not read PHY dev address\n", __func__);
118		return;
119	}
120
121	/*
122	 * Enable RGMII delay on Tx and Rx for CPU port
123	 * Ref: sec 4.7.2 of chip datasheet
124	 */
125	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
126	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
127	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
128	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
129	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
130
131	/* reset the phy */
132	miiphy_reset(name, devadr);
133
134	debug("88E1116 Initialized on %s\n", name);
135}
136#endif /* CONFIG_RESET_PHY_R */
137