1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
4 * Copyright (C) 2012
5 * David Purdy <david.c.purdy@gmail.com>
6 *
7 * Based on Kirkwood support:
8 * (C) Copyright 2009
9 * Marvell Semiconductor <www.marvell.com>
10 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11 */
12
13#include <common.h>
14#include <init.h>
15#include <log.h>
16#include <netdev.h>
17#include <asm/arch/cpu.h>
18#include <asm/arch/soc.h>
19#include <asm/arch/mpp.h>
20#include <asm/global_data.h>
21#include <linux/bitops.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
25/* GPIO configuration */
26#define POGO_E02_OE_LOW			(~(0))
27#define POGO_E02_OE_HIGH		(~(0))
28#define POGO_E02_OE_VAL_LOW		BIT(29)
29#define POGO_E02_OE_VAL_HIGH		0
30
31int board_early_init_f(void)
32{
33	/*
34	 * default gpio configuration
35	 * There are maximum 64 gpios controlled through 2 sets of registers
36	 * the  below configuration configures mainly initial LED status
37	 */
38	mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
39			  POGO_E02_OE_VAL_HIGH,
40			  POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
41
42	/* Multi-Purpose Pins Functionality configuration */
43	static const u32 kwmpp_config[] = {
44		MPP0_NF_IO2,
45		MPP1_NF_IO3,
46		MPP2_NF_IO4,
47		MPP3_NF_IO5,
48		MPP4_NF_IO6,
49		MPP5_NF_IO7,
50		MPP6_SYSRST_OUTn,
51		MPP7_GPO,
52		MPP8_UART0_RTS,
53		MPP9_UART0_CTS,
54		MPP10_UART0_TXD,
55		MPP11_UART0_RXD,
56		MPP12_SD_CLK,
57		MPP13_SD_CMD,
58		MPP14_SD_D0,
59		MPP15_SD_D1,
60		MPP16_SD_D2,
61		MPP17_SD_D3,
62		MPP18_NF_IO0,
63		MPP19_NF_IO1,
64		MPP29_TSMP9,	/* USB Power Enable */
65		MPP48_GPIO,	/* LED green */
66		MPP49_GPIO,	/* LED orange */
67		0
68	};
69	kirkwood_mpp_conf(kwmpp_config, NULL);
70	return 0;
71}
72
73int board_eth_init(struct bd_info *bis)
74{
75	return cpu_eth_init(bis);
76}
77
78int board_init(void)
79{
80	/* Boot parameters address */
81	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
82
83	return 0;
84}
85