1193323Sed// SPDX-License-Identifier: GPL-2.0 2193323Sed/* 3193323Sed * https://beagleplay.org/ 4193323Sed * 5193323Sed * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ 6193323Sed * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation 7193323Sed */ 8193323Sed 9193323Sed#include <efi_loader.h> 10193323Sed#include <cpu_func.h> 11193323Sed#include <env.h> 12193323Sed#include <fdt_support.h> 13193323Sed#include <spl.h> 14193323Sed 15193323Sed#include <asm/arch/hardware.h> 16249423Sdim 17249423SdimDECLARE_GLOBAL_DATA_PTR; 18193323Sed 19198090Srdivackystruct efi_fw_image fw_images[] = { 20249423Sdim { 21249423Sdim .image_type_id = BEAGLEPLAY_TIBOOT3_IMAGE_GUID, 22249423Sdim .fw_name = u"BEAGLEPLAY_TIBOOT3", 23249423Sdim .image_index = 1, 24249423Sdim }, 25249423Sdim { 26193323Sed .image_type_id = BEAGLEPLAY_SPL_IMAGE_GUID, 27193323Sed .fw_name = u"BEAGLEPLAY_SPL", 28193323Sed .image_index = 2, 29193323Sed }, 30193323Sed { 31193323Sed .image_type_id = BEAGLEPLAY_UBOOT_IMAGE_GUID, 32193323Sed .fw_name = u"BEAGLEPLAY_UBOOT", 33249423Sdim .image_index = 3, 34249423Sdim } 35249423Sdim}; 36249423Sdim 37249423Sdimstruct efi_capsule_update_info update_info = { 38249423Sdim .dfu_string = "mmc 0=tiboot3.bin raw 0 2000 mmcpart 1;" 39249423Sdim "tispl.bin fat 0 1;u-boot.img fat 0 1", 40249423Sdim .num_images = ARRAY_SIZE(fw_images), 41249423Sdim .images = fw_images, 42249423Sdim}; 43249423Sdim 44249423Sdim#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) 45249423Sdimvoid set_dfu_alt_info(char *interface, char *devstr) 46249423Sdim{ 47249423Sdim if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) 48249423Sdim env_set("dfu_alt_info", update_info.dfu_string); 49249423Sdim} 50249423Sdim#endif 51249423Sdim 52249423Sdimint board_init(void) 53249423Sdim{ 54249423Sdim return 0; 55249423Sdim} 56249423Sdim 57249423Sdimint dram_init(void) 58249423Sdim{ 59249423Sdim return fdtdec_setup_mem_size_base(); 60249423Sdim} 61193323Sed 62193323Sedint dram_init_banksize(void) 63193323Sed{ 64218893Sdim return fdtdec_setup_memory_banksize(); 65218893Sdim} 66263508Sdim 67249423Sdim#ifdef CONFIG_BOARD_LATE_INIT 68218893Sdimint board_late_init(void) 69218893Sdim{ 70193323Sed char fdtfile[50]; 71193323Sed 72193323Sed snprintf(fdtfile, sizeof(fdtfile), "%s/%s.dtb", 73234353Sdim CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_DEVICE_TREE); 74234353Sdim 75234353Sdim env_set("fdtfile", fdtfile); 76234353Sdim 77234353Sdim return 0; 78234353Sdim} 79234353Sdim#endif 80234353Sdim 81234353Sdim#ifdef CONFIG_SPL_BOARD_INIT 82234353Sdim 83234353Sdim/* 84234353Sdim * Enable the 32k Crystal: needed for accurate 32k clock 85234353Sdim * and external clock sources such as wlan 32k input clock 86234353Sdim * supplied from the SoC to the wlan chip. 87234353Sdim * 88234353Sdim * The trim setup can be very highly board type specific choice of the crystal 89234353Sdim * So this is done in the board file, though, in this case, no specific trim 90234353Sdim * is necessary. 91234353Sdim */ 92249423Sdimstatic void crystal_32k_enable(void) 93249423Sdim{ 94249423Sdim /* Only mess with 32k at the start of boot from R5 */ 95249423Sdim if (IS_ENABLED(CONFIG_CPU_V7R)) { 96249423Sdim /* 97249423Sdim * We have external 32k crystal, so lets enable it (0x0) 98249423Sdim * and disable bypass (0x0) 99249423Sdim */ 100234353Sdim writel(0x0, MCU_CTRL_LFXOSC_CTRL); 101249423Sdim 102249423Sdim /* Add any crystal specific TRIM needed here.. */ 103234353Sdim 104249423Sdim /* Make sure to mux the SoC 32k from the crystal */ 105249423Sdim writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, 106249423Sdim MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); 107234353Sdim } 108234353Sdim} 109249423Sdim 110249423Sdimstatic void debounce_configure(void) 111249423Sdim{ 112193323Sed /* Configure debounce one time from R5 */ 113 if (IS_ENABLED(CONFIG_CPU_V7R)) { 114 /* 115 * Setup debounce time registers. 116 * arbitrary values. Times are approx 117 */ 118 /* 1.9ms debounce @ 32k */ 119 writel(0x1, CTRLMMR_DBOUNCE_CFG(1)); 120 /* 5ms debounce @ 32k */ 121 writel(0x5, CTRLMMR_DBOUNCE_CFG(2)); 122 /* 20ms debounce @ 32k */ 123 writel(0x14, CTRLMMR_DBOUNCE_CFG(3)); 124 /* 46ms debounce @ 32k */ 125 writel(0x18, CTRLMMR_DBOUNCE_CFG(4)); 126 /* 100ms debounce @ 32k */ 127 writel(0x1c, CTRLMMR_DBOUNCE_CFG(5)); 128 /* 156ms debounce @ 32k */ 129 writel(0x1f, CTRLMMR_DBOUNCE_CFG(6)); 130 } 131} 132 133void spl_board_init(void) 134{ 135 crystal_32k_enable(); 136 debounce_configure(); 137} 138#endif 139