1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 * Copyright 2022 Linaro
5 */
6
7#include <common.h>
8#include <command.h>
9#include <cpu_func.h>
10#include <errno.h>
11#include <fsl_esdhc_imx.h>
12#include <hang.h>
13#include <image.h>
14#include <init.h>
15#include <log.h>
16#include <mmc.h>
17#include <spl.h>
18#include <asm/io.h>
19#include <asm/arch/clock.h>
20#include <asm/arch/ddr.h>
21#include <asm/arch/imx8mp_pins.h>
22#include <asm/arch/sys_proto.h>
23#include <asm/mach-imx/boot_mode.h>
24#include <asm/mach-imx/gpio.h>
25#include <asm/mach-imx/iomux-v3.h>
26#include <asm/mach-imx/mxc_i2c.h>
27#include <dm/uclass.h>
28#include <linux/delay.h>
29#include <power/pmic.h>
30#include <power/pca9450.h>
31
32DECLARE_GLOBAL_DATA_PTR;
33
34int spl_board_boot_device(enum boot_device boot_dev_spl)
35{
36#ifdef CONFIG_SPL_BOOTROM_SUPPORT
37	return BOOT_DEVICE_BOOTROM;
38#else
39	switch (boot_dev_spl) {
40	case SD1_BOOT:
41	case MMC1_BOOT:
42	case SD2_BOOT:
43	case MMC2_BOOT:
44		return BOOT_DEVICE_MMC1;
45	case SD3_BOOT:
46	case MMC3_BOOT:
47		return BOOT_DEVICE_MMC2;
48	case QSPI_BOOT:
49		return BOOT_DEVICE_NOR;
50	case NAND_BOOT:
51		return BOOT_DEVICE_NAND;
52	case USB_BOOT:
53		return BOOT_DEVICE_BOARD;
54	default:
55		return BOOT_DEVICE_NONE;
56	}
57#endif
58}
59
60void spl_dram_init(void)
61{
62	ddr_init(&dram_timing);
63}
64
65#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
66#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
67struct i2c_pads_info i2c_pad_info1 = {
68	.scl = {
69		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
70		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
71		.gp = IMX_GPIO_NR(5, 14),
72	},
73	.sda = {
74		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
75		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
76		.gp = IMX_GPIO_NR(5, 15),
77	},
78};
79
80#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
81#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
82
83#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
84			 PAD_CTL_PE |				    \
85			 PAD_CTL_FSEL2)
86#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
87#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS | \
88			   PAD_CTL_DSE4)
89
90static const iomux_v3_cfg_t usdhc3_pads[] = {
91	MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92	MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93	MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94	MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95	MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96	MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97	MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98	MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99	MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100	MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101};
102
103static const iomux_v3_cfg_t usdhc2_pads[] = {
104	MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105	MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106	MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107	MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108	MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109	MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110	MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
111	MX8MP_PAD_SD2_CD_B__GPIO2_IO12    | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
112};
113
114#ifndef USDHC3_BASE_ADDR
115#define USDHC3_BASE_ADDR	0x30B60000
116#endif
117
118static struct fsl_esdhc_cfg usdhc_cfg[2] = {
119	{USDHC2_BASE_ADDR, 0, 4},
120	{USDHC3_BASE_ADDR, 0, 8},
121};
122
123int board_mmc_init(struct bd_info *bis)
124{
125	int i, ret;
126	/*
127	 * According to the board_mmc_init() the following map is done:
128	 * (U-Boot device node)    (Physical Port)
129	 * mmc0                    USDHC1
130	 * mmc1                    USDHC2
131	 */
132	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
133		switch (i) {
134		case 0:
135			init_clk_usdhc(1);
136			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
137			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
138							 ARRAY_SIZE(usdhc2_pads));
139			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
140			gpio_direction_output(USDHC2_PWR_GPIO, 0);
141			udelay(500);
142			gpio_direction_output(USDHC2_PWR_GPIO, 1);
143			gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
144			gpio_direction_input(USDHC2_CD_GPIO);
145			break;
146		case 1:
147			init_clk_usdhc(2);
148			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
149			imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
150							 ARRAY_SIZE(usdhc3_pads));
151			break;
152		default:
153			printf("Warning: you configured more USDHC controllers");
154			printf("(%d) than supported by the board\n", i + 1);
155			return -EINVAL;
156		}
157
158		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
159		if (ret)
160			return ret;
161	}
162
163	return 0;
164}
165
166int board_mmc_getcd(struct mmc *mmc)
167{
168	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
169	int ret = 0;
170
171	switch (cfg->esdhc_base) {
172	default:
173		break;
174	case USDHC2_BASE_ADDR:
175		ret = !gpio_get_value(USDHC2_CD_GPIO);
176		return ret;
177	}
178
179	return 1;
180}
181
182int power_init_board(void)
183{
184	struct udevice *pdev;
185	int ret;
186
187	ret = pmic_get("pca9450@25", &pdev);
188	if (ret == -ENODEV) {
189		printf("No pmic\n");
190		return 0;
191	}
192	if (ret != 0)
193		return ret;
194
195	/* BUCKxOUT_DVS0/1 control BUCK123 output */
196	pmic_reg_write(pdev, PCA9450_BUCK123_DVS, 0x29);
197
198	/*
199	 * increase VDD_SOC to typical value 0.95V before first
200	 * DRAM access, set DVS1 to 0.85v for suspend.
201	 * Enable DVS control through PMIC_STBY_REQ and
202	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
203	 */
204	pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS0, 0x1C);
205	pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS1, 0x14);
206	pmic_reg_write(pdev, PCA9450_BUCK1CTRL, 0x59);
207
208	/* Kernel uses OD/OD freq for SOC */
209	/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
210	pmic_reg_write(pdev, PCA9450_BUCK2OUT_DVS0, 0x1C);
211
212	/* Forced enable the I2C level translator*/
213	pmic_reg_write(pdev, PCA9450_CONFIG2, 0x03);
214
215	return 0;
216}
217
218void spl_board_init(void)
219{
220	puts("Normal Boot\n");
221}
222
223#ifdef CONFIG_SPL_LOAD_FIT
224int board_fit_config_name_match(const char *name)
225{
226	/* Just empty function now - can't decide what to choose */
227	debug("%s: %s\n", __func__, name);
228
229	return 0;
230}
231#endif
232
233void board_init_f(ulong dummy)
234{
235	int ret;
236
237	arch_cpu_init();
238
239	board_early_init_f();
240
241	timer_init();
242
243	ret = spl_early_init();
244	if (ret) {
245		debug("spl_init() failed: %d\n", ret);
246		hang();
247	}
248
249	preloader_console_init();
250
251	enable_tzc380();
252
253	power_init_board();
254
255	/* DDR initialization */
256	spl_dram_init();
257}
258