1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019 NXP 4 * Copyright 2022 Linaro 5 */ 6 7#include <common.h> 8#include <dwc3-uboot.h> 9#include <efi.h> 10#include <efi_loader.h> 11#include <errno.h> 12#include <miiphy.h> 13#include <netdev.h> 14#include <spl.h> 15#include <usb.h> 16#include <asm/io.h> 17#include <asm/mach-imx/iomux-v3.h> 18#include <asm-generic/gpio.h> 19#include <asm/arch/imx8mp_pins.h> 20#include <asm/arch/sys_proto.h> 21#include <asm/mach-imx/gpio.h> 22#include <asm/mach-imx/mxc_i2c.h> 23#include <asm/arch/clock.h> 24#include <asm/mach-imx/dma.h> 25#include <linux/delay.h> 26#include <linux/kernel.h> 27#include <power/pmic.h> 28 29DECLARE_GLOBAL_DATA_PTR; 30 31#ifdef CONFIG_NAND_MXS 32static void setup_gpmi_nand(void) 33{ 34 init_nand_clk(); 35} 36#endif 37 38#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) 39struct efi_fw_image fw_images[] = { 40#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G) 41 { 42 .image_type_id = IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID, 43 .fw_name = u"IMX8MP-RSB3720-FIT", 44 .image_index = 1, 45 }, 46#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G) 47 { 48 .image_type_id = IMX8MP_RSB3720A1_6G_FIT_IMAGE_GUID, 49 .fw_name = u"IMX8MP-RSB3720-FIT", 50 .image_index = 1, 51 }, 52#endif 53}; 54 55struct efi_capsule_update_info update_info = { 56 .dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1", 57 .num_images = ARRAY_SIZE(fw_images), 58 .images = fw_images, 59}; 60 61#endif /* EFI_HAVE_CAPSULE_SUPPORT */ 62 63 64int board_early_init_f(void) 65{ 66 init_uart_clk(2); 67 68 return 0; 69} 70 71#ifdef CONFIG_OF_BOARD_SETUP 72int ft_board_setup(void *blob, struct bd_info *bd) 73{ 74 return 0; 75} 76#endif 77 78#ifdef CONFIG_FEC_MXC 79#define FEC_RST_PAD IMX_GPIO_NR(4, 2) 80static const iomux_v3_cfg_t fec1_rst_pads[] = { 81 MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), 82}; 83 84static void setup_iomux_fec(void) 85{ 86 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, 87 ARRAY_SIZE(fec1_rst_pads)); 88 89 gpio_request(FEC_RST_PAD, "fec1_rst"); 90 gpio_direction_output(FEC_RST_PAD, 0); 91 mdelay(15); 92 gpio_direction_output(FEC_RST_PAD, 1); 93 mdelay(100); 94} 95 96static int setup_fec(void) 97{ 98 struct iomuxc_gpr_base_regs *gpr = 99 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 100 101 setup_iomux_fec(); 102 103 /* Enable RGMII TX clk output */ 104 setbits_le32(&gpr->gpr[1], BIT(22)); 105 106 return 0; 107} 108#endif /* CONFIG_FEC_MXC */ 109 110#ifdef CONFIG_DWC_ETH_QOS 111#define EQOS_RST_PAD IMX_GPIO_NR(4, 22) 112static const iomux_v3_cfg_t eqos_rst_pads[] = { 113 MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 114}; 115 116static void setup_eqos(void) 117{ 118 imx_iomux_v3_setup_multiple_pads(eqos_rst_pads, 119 ARRAY_SIZE(eqos_rst_pads)); 120 121 gpio_request(EQOS_RST_PAD, "eqos_rst"); 122 gpio_direction_output(EQOS_RST_PAD, 0); 123 mdelay(15); 124 gpio_direction_output(EQOS_RST_PAD, 1); 125 mdelay(100); 126} 127#endif /* CONFIG_DWC_ETH_QOS */ 128 129int board_phy_config(struct phy_device *phydev) 130{ 131 if (IS_ENABLED(CONFIG_FEC_MXC) || IS_ENABLED(CONFIG_DWC_ETH_QOS)) { 132 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 133 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 134 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 135 136 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); 137 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); 138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 140 141 if (phydev->drv->config) 142 phydev->drv->config(phydev); 143 } 144 145 return 0; 146} 147 148#define DISPMIX 13 149#define MIPI 15 150 151#define WDOG_TRIG IMX_GPIO_NR(4, 20) 152 153static iomux_v3_cfg_t wdt_trig[] = { 154 MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), 155}; 156 157static void setup_iomux_wdt(void) 158{ 159 imx_iomux_v3_setup_multiple_pads(wdt_trig, ARRAY_SIZE(wdt_trig)); 160 gpio_request(WDOG_TRIG, "wdt_trig"); 161 gpio_direction_output(WDOG_TRIG, 1); 162} 163 164int board_init(void) 165{ 166#ifdef CONFIG_FEC_MXC 167 setup_fec(); 168#endif 169 170#ifdef CONFIG_DWC_ETH_QOS 171 /* clock, pin, gpr */ 172 setup_eqos(); 173#endif 174 175#ifdef CONFIG_NAND_MXS 176 setup_gpmi_nand(); 177#endif 178 179 setup_iomux_wdt(); 180 181 return 0; 182} 183 184int board_late_init(void) 185{ 186 if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { 187 env_set("board_name", "RSB3720A1"); 188 env_set("board_rev", "iMX8MP"); 189 } 190 191 return 0; 192} 193 194#ifdef CONFIG_SPL_MMC 195#define UBOOT_RAW_SECTOR_OFFSET 0x40 196unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, 197 unsigned long raw_sector) 198{ 199 u32 boot_dev = spl_boot_device(); 200 201 switch (boot_dev) { 202 case BOOT_DEVICE_MMC2: 203 return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET; 204 default: 205 return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; 206 } 207} 208#endif /* CONFIG_SPL_MMC */ 209