1178825Sdfr# Synology DS109 2233294Sstas 3233294Sstasinterface ftdi 4233294Sstasftdi_vid_pid 0x0403 0x6010 5178825Sdfr 6233294Sstasftdi_layout_init 0x0008 0x000b 7233294Sstasftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 8233294Sstasftdi_layout_signal nSRST -data 0x0040 -oe 0x0040 9178825Sdfr 10233294Sstasadapter_khz 2000 11233294Sstas 12178825Sdfr# length of reset signal: [ms] 13233294Sstasadapter_nsrst_assert_width 1000 14233294Sstas 15233294Sstas# don't talk to JTAG after reset for: [ms] 16178825Sdfradapter_nsrst_delay 200 17233294Sstas 18233294Sstassource [find target/feroceon.cfg] 19233294Sstas 20178825Sdfrreset_config trst_and_srst srst_nogate 21233294Sstas 22233294Sstasproc ds109_init { } { 23233294Sstas 24233294Sstas # We need to assert DBGRQ while holding nSRST down. 25233294Sstas # However DBGACK will be set only when nSRST is released. 26233294Sstas # Furthermore, the JTAG interface doesn't respond at all when 27233294Sstas # the CPU is in the WFI (wait for interrupts) state, so it is 28233294Sstas # possible that initial tap examination failed. So let's 29233294Sstas # re-examine the target again here when nSRST is asserted which 30233294Sstas # should then succeed. 31233294Sstas jtag_reset 0 1 32178825Sdfr feroceon.cpu arp_examine 33178825Sdfr halt 0 34178825Sdfr jtag_reset 0 0 35178825Sdfr wait_halt 36233294Sstas #reset run 37178825Sdfr #soft_reset_halt 38178825Sdfr 39178825Sdfr arm mcr 15 0 0 1 0 0x00052078 40178825Sdfr 41178825Sdfr mww 0xD00100e0 0x1b1b1b9b ;# 42178825Sdfr mww 0xD0020134 0xbbbbbbbb ;# 43178825Sdfr mww 0xD0020138 0x00bbbbbb ;# 44178825Sdfr mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register 45178825Sdfr mww 0xD0001404 0x39743000 ;# Dunit Control Low Register 46178825Sdfr mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register 47178825Sdfr mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register 48178825Sdfr mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register 49178825Sdfr mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register 50178825Sdfr mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register 51178825Sdfr mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register 52178825Sdfr mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register 53178825Sdfr mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register 54178825Sdfr mww 0xD0001428 0x00085520 ;# Dunit Control High Register 55178825Sdfr mww 0xD000147c 0x00008552 ;# Dunit Control High Register 56178825Sdfr mww 0xD0001500 0x00000000 ;# 57178825Sdfr mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register 58178825Sdfr mww 0xD0001508 0x10000000 ;# CS1n Base Register 59178825Sdfr mww 0xD000150C 0x00000000 ;# CS1n Size Register 60178825Sdfr mww 0xD0001510 0x20000000 ;# 61178825Sdfr mww 0xD0001514 0x00000000 ;# CS2n Size Register 62178825Sdfr mww 0xD000151C 0x00000000 ;# CS3n Size Register 63178825Sdfr mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register 64178825Sdfr mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister 65178825Sdfr mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register 66178825Sdfr mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register 67178825Sdfr mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register 68178825Sdfr mww 0xD0020204 0x00000000 ;# " 69178825Sdfr mww 0xD0020204 0x00000000 ;# " 70178825Sdfr mww 0xD0020204 0x00000000 ;# " 71178825Sdfr mww 0xD0020204 0x00000000 ;# " 72178825Sdfr mww 0xD0020204 0x00000000 ;# " 73178825Sdfr mww 0xD0020204 0x00000000 ;# " 74178825Sdfr mww 0xD0020204 0x00000000 ;# " 75178825Sdfr mww 0xD0020204 0x00000000 ;# " 76178825Sdfr mww 0xD0020204 0x00000000 ;# " 77178825Sdfr mww 0xD0020204 0x00000000 ;# " 78178825Sdfr mww 0xD0020204 0x00000000 ;# " 79178825Sdfr mww 0xD0020204 0x00000000 ;# " 80178825Sdfr mww 0xD0020204 0x00000000 ;# " 81178825Sdfr mww 0xD0020204 0x00000000 ;# " 82178825Sdfr mww 0xD0020204 0x00000000 ;# " 83178825Sdfr mww 0xD0020204 0x00000000 ;# " 84178825Sdfr mww 0xD0020204 0x00000000 ;# " 85178825Sdfr mww 0xD0020204 0x00000000 ;# " 86 mww 0xD0020204 0x00000000 ;# " 87 mww 0xD0020204 0x00000000 ;# " 88 mww 0xD0020204 0x00000000 ;# " 89 mww 0xD0020204 0x00000000 ;# " 90 mww 0xD0020204 0x00000000 ;# " 91 mww 0xD0020204 0x00000000 ;# " 92 mww 0xD0020204 0x00000000 ;# " 93 mww 0xD0020204 0x00000000 ;# " 94 mww 0xD0020204 0x00000000 ;# " 95 mww 0xD0020204 0x00000000 ;# " 96 mww 0xD0020204 0x00000000 ;# " 97 mww 0xD0020204 0x00000000 ;# " 98 mww 0xD0020204 0x00000000 ;# " 99 mww 0xD0020204 0x00000000 ;# " 100 mww 0xD0020204 0x00000000 ;# " 101 mww 0xD0020204 0x00000000 ;# " 102 mww 0xD0020204 0x00000000 ;# " 103 mww 0xD0020204 0x00000000 ;# " 104 105 mww 0xD0010000 0x01111111 ;# MPP 0 to 7 106 mww 0xD0010004 0x11113322 ;# MPP 8 to 15 107 mww 0xD0010008 0x00001111 ;# MPP 16 to 23 108} 109 110proc ds109_load { } { 111 # load u-Boot into RAM and execute it 112 ds109_init 113 load_image u-boot.bin 0x00600000 bin 114 resume 0x00600000 115} 116