1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com> 4 * 5 * Based on sheevaplug.c originally written by 6 * Prafulla Wadaskar <prafulla@marvell.com> 7 * (C) Copyright 2009 8 * Marvell Semiconductor <www.marvell.com> 9 */ 10 11#include <common.h> 12#include <init.h> 13#include <miiphy.h> 14#include <net.h> 15#include <asm/global_data.h> 16#include <asm/mach-types.h> 17#include <asm/arch/soc.h> 18#include <asm/arch/mpp.h> 19#include <asm/arch/cpu.h> 20#include <asm/io.h> 21 22DECLARE_GLOBAL_DATA_PTR; 23 24int board_early_init_f(void) 25{ 26 /* 27 * default gpio configuration 28 */ 29 mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH, 30 NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH); 31 32 /* Multi-Purpose Pins Functionality configuration */ 33 static const u32 kwmpp_config[] = { 34 MPP0_NF_IO2, 35 MPP1_NF_IO3, 36 MPP2_NF_IO4, 37 MPP3_NF_IO5, 38 MPP4_NF_IO6, 39 MPP5_NF_IO7, 40 MPP6_SYSRST_OUTn, 41 MPP7_SPI_SCn, 42 MPP8_TW_SDA, 43 MPP9_TW_SCK, 44 MPP10_UART0_TXD, 45 MPP11_UART0_RXD, 46 MPP12_GPO, 47 MPP13_GPIO, 48 MPP14_GPIO, 49 MPP15_SATA0_ACTn, 50 MPP16_SATA1_ACTn, 51 MPP17_SATA0_PRESENTn, 52 MPP18_NF_IO0, 53 MPP19_NF_IO1, 54 MPP20_GPIO, 55 MPP21_GPIO, 56 MPP22_GPIO, 57 MPP23_GPIO, 58 MPP24_GPIO, 59 MPP25_GPIO, 60 MPP26_GPIO, 61 MPP27_GPIO, 62 MPP28_GPIO, 63 MPP29_GPIO, 64 MPP30_GPIO, 65 MPP31_GPIO, 66 MPP32_GPIO, 67 MPP33_GPIO, 68 MPP34_GPIO, 69 MPP35_GPIO, 70 0 71 }; 72 kirkwood_mpp_conf(kwmpp_config, NULL); 73 return 0; 74} 75 76int board_init(void) 77{ 78 /* 79 * arch number of board 80 */ 81 gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS; 82 83 /* adress of boot parameters */ 84 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 85 86 return 0; 87} 88 89#ifdef CONFIG_RESET_PHY_R 90/* Configure and enable MV88E1116 PHY */ 91void reset_phy(void) 92{ 93 u16 reg; 94 u16 devadr; 95 char *name = "egiga0"; 96 97 if (miiphy_set_current_dev(name)) 98 return; 99 100 /* command to read PHY dev address */ 101 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { 102 printf("Err..%s could not read PHY dev address\n", __func__); 103 return; 104 } 105 106 /* 107 * Enable RGMII delay on Tx and Rx for CPU port 108 * Ref: sec 4.7.2 of chip datasheet 109 */ 110 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 111 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 112 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 113 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 114 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 115 116 /* reset the phy */ 117 miiphy_reset(name, devadr); 118 119 printf("88E1116 Initialized on %s\n", name); 120} 121#endif /* CONFIG_RESET_PHY_R */ 122