1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2009
4 * Net Insight <www.netinsight.net>
5 * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
6 *
7 * Based on sheevaplug.c:
8 * (C) Copyright 2009
9 * Marvell Semiconductor <www.marvell.com>
10 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11 */
12
13#include <common.h>
14#include <init.h>
15#include <miiphy.h>
16#include <net.h>
17#include <asm/global_data.h>
18#include <asm/mach-types.h>
19#include <asm/arch/cpu.h>
20#include <asm/arch/soc.h>
21#include <asm/arch/mpp.h>
22#include "openrd.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26int board_early_init_f(void)
27{
28	/*
29	 * default gpio configuration
30	 * There are maximum 64 gpios controlled through 2 sets of registers
31	 * the  below configuration configures mainly initial LED status
32	 */
33	mvebu_config_gpio(OPENRD_OE_VAL_LOW,
34			  OPENRD_OE_VAL_HIGH,
35			  OPENRD_OE_LOW, OPENRD_OE_HIGH);
36
37	/* Multi-Purpose Pins Functionality configuration */
38	static const u32 kwmpp_config[] = {
39		MPP0_NF_IO2,
40		MPP1_NF_IO3,
41		MPP2_NF_IO4,
42		MPP3_NF_IO5,
43		MPP4_NF_IO6,
44		MPP5_NF_IO7,
45		MPP6_SYSRST_OUTn,
46		MPP7_GPO,
47		MPP8_TW_SDA,
48		MPP9_TW_SCK,
49		MPP10_UART0_TXD,
50		MPP11_UART0_RXD,
51		MPP12_SD_CLK,
52		MPP13_SD_CMD, /* Alt UART1_TXD */
53		MPP14_SD_D0,  /* Alt UART1_RXD */
54		MPP15_SD_D1,
55		MPP16_SD_D2,
56		MPP17_SD_D3,
57		MPP18_NF_IO0,
58		MPP19_NF_IO1,
59		MPP20_GE1_0,
60		MPP21_GE1_1,
61		MPP22_GE1_2,
62		MPP23_GE1_3,
63		MPP24_GE1_4,
64		MPP25_GE1_5,
65		MPP26_GE1_6,
66		MPP27_GE1_7,
67		MPP28_GPIO,
68		MPP29_TSMP9,
69		MPP30_GE1_10,
70		MPP31_GE1_11,
71		MPP32_GE1_12,
72		MPP33_GE1_13,
73		MPP34_GPIO,   /* UART1 / SD sel */
74		MPP35_TDM_CH0_TX_QL,
75		MPP36_TDM_SPI_CS1,
76		MPP37_TDM_CH2_TX_QL,
77		MPP38_TDM_CH2_RX_QL,
78		MPP39_AUDIO_I2SBCLK,
79		MPP40_AUDIO_I2SDO,
80		MPP41_AUDIO_I2SLRC,
81		MPP42_AUDIO_I2SMCLK,
82		MPP43_AUDIO_I2SDI,
83		MPP44_AUDIO_EXTCLK,
84		MPP45_TDM_PCLK,
85		MPP46_TDM_FS,
86		MPP47_TDM_DRX,
87		MPP48_TDM_DTX,
88		MPP49_TDM_CH0_RX_QL,
89		0
90	};
91
92	kirkwood_mpp_conf(kwmpp_config, NULL);
93	return 0;
94}
95
96int board_init(void)
97{
98	/*
99	 * arch number of board
100	 */
101#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
102	gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
103#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
104	gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
105#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
106	gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
107#endif
108
109	/* adress of boot parameters */
110	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
111	return 0;
112}
113
114#ifdef CONFIG_RESET_PHY_R
115/* Configure and enable MV88E1116/88E1121 PHY */
116void mv_phy_init(char *name)
117{
118	u16 reg;
119	u16 devadr;
120
121	if (miiphy_set_current_dev(name))
122		return;
123
124	/* command to read PHY dev address */
125	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
126		printf("Err..%s could not read PHY dev address\n", __func__);
127		return;
128	}
129
130	/*
131	 * Enable RGMII delay on Tx and Rx for CPU port
132	 * Ref: sec 4.7.2 of chip datasheet
133	 */
134	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
135	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
136	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
137	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
138	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
139
140	/* reset the phy */
141	miiphy_reset(name, devadr);
142
143	printf("Initialized on %s\n", name);
144}
145
146void reset_phy(void)
147{
148	mv_phy_init("egiga0");
149
150#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
151	/* Kirkwood ethernet driver is written with the assumption that in case
152	 * of multiple PHYs, their addresses are consecutive. But unfortunately
153	 * in case of OpenRD-Client, PHY addresses are not consecutive.*/
154	miiphy_write("egiga1", 0xEE, 0xEE, 24);
155#endif
156
157#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
158	defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
159	/* configure and initialize both PHY's */
160	mv_phy_init("egiga1");
161#endif
162}
163#endif /* CONFIG_RESET_PHY_R */
164