1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 */
5
6#include <common.h>
7#include <i2c.h>
8#include <init.h>
9#include <miiphy.h>
10#include <net.h>
11#include <netdev.h>
12#include <asm/global_data.h>
13#include <asm/io.h>
14#include <asm/arch/cpu.h>
15#include <asm/arch/soc.h>
16#include <linux/bitops.h>
17
18#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
19#include <../serdes/a38x/high_speed_env_spec.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23/*
24 * Those values and defines are taken from the Marvell U-Boot version
25 * "u-boot-2013.01-2016_T1.0.eng_drop_v10"
26 */
27#define DB_AMC_88F68XX_GPP_OUT_ENA_LOW					\
28	(~(BIT(29)))
29#define DB_AMC_88F68XX_GPP_OUT_ENA_MID					\
30	(~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
31#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW	(BIT(29))
32#define DB_AMC_88F68XX_GPP_OUT_VAL_MID	0x0
33#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH	0x0
34#define DB_AMC_88F68XX_GPP_POL_LOW	0x0
35#define DB_AMC_88F68XX_GPP_POL_MID	0x0
36
37static struct serdes_map board_serdes_map[] = {
38	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
39	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
40	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
41	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
42	{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
43	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
44};
45
46int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
47{
48	*serdes_map_array = board_serdes_map;
49	*count = ARRAY_SIZE(board_serdes_map);
50	return 0;
51}
52
53/*
54 * Define the DDR layout / topology here in the board file. This will
55 * be used by the DDR3 init code in the SPL U-Boot version to configure
56 * the DDR3 controller.
57 */
58static struct mv_ddr_topology_map board_topology_map = {
59	DEBUG_LEVEL_ERROR,
60	0x1, /* active interfaces */
61	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
62	{ { { {0x1, 0, 0, 0},
63	      {0x1, 0, 0, 0},
64	      {0x1, 0, 0, 0},
65	      {0x1, 0, 0, 0},
66	      {0x1, 0, 0, 0} },
67	    SPEED_BIN_DDR_1866L,	/* speed_bin */
68	    MV_DDR_DEV_WIDTH_8BIT,	/* memory_width */
69	    MV_DDR_DIE_CAP_2GBIT,	/* mem_size */
70	    MV_DDR_FREQ_800,		/* frequency */
71	    0, 0,			/* cas_wl cas_l */
72	    MV_DDR_TEMP_LOW,		/* temperature */
73	    MV_DDR_TIM_DEFAULT} },	/* timing */
74	BUS_MASK_32BIT,			/* Busses mask */
75	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
76	NOT_COMBINED,			/* ddr twin-die combined */
77	{ {0} },			/* raw spd data */
78	{0}				/* timing parameters */
79};
80
81struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
82{
83	/* Return the board topology as defined in the board code */
84	return &board_topology_map;
85}
86
87int board_early_init_f(void)
88{
89	/* Configure MPP */
90	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
91	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
92	writel(0x55066011, MVEBU_MPP_BASE + 0x08);
93	writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
94	writel(0x05055555, MVEBU_MPP_BASE + 0x10);
95	writel(0x01106565, MVEBU_MPP_BASE + 0x14);
96	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
97	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
98
99	/* Set GPP Out value */
100	writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
101	writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
102
103	/* Set GPP Polarity */
104	writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
105	writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
106
107	/* Set GPP Out Enable */
108	writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
109	writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
110
111	return 0;
112}
113
114int board_init(void)
115{
116	/* adress of boot parameters */
117	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
118
119	return 0;
120}
121
122int checkboard(void)
123{
124	puts("Board: Marvell DB-88F6820-AMC\n");
125
126	return 0;
127}
128
129int board_eth_init(struct bd_info *bis)
130{
131	cpu_eth_init(bis); /* Built in controller(s) come first */
132	return pci_eth_init(bis);
133}
134