1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * board.c
4 *
5 * Board functions for B&R BRXRE1 Board
6 *
7 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
9 *
10 */
11#include <common.h>
12#include <env.h>
13#include <errno.h>
14#include <init.h>
15#include <spl.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/hardware.h>
18#include <asm/arch/omap.h>
19#include <asm/arch/ddr_defs.h>
20#include <asm/arch/clock.h>
21#include <asm/arch/gpio.h>
22#include <asm/arch/sys_proto.h>
23#include <asm/arch/mem.h>
24#include <asm/global_data.h>
25#include <asm/io.h>
26#include <asm/emif.h>
27#include <asm/gpio.h>
28#include <dm.h>
29#include <power/tps65217.h>
30#include "../common/bur_common.h"
31#include "../common/br_resetc.h"
32
33/* -------------------------------------------------------------------------*/
34/* -- defines for used GPIO Hardware -- */
35#define ESC_KEY					(0 + 19)
36#define LCD_PWR					(0 + 5)
37
38#define	RSTCTRL_FORCE_PWR_NEN			0x04
39#define	RSTCTRL_CAN_STB				0x40
40
41DECLARE_GLOBAL_DATA_PTR;
42
43#if defined(CONFIG_SPL_BUILD)
44static const struct ddr_data ddr3_data = {
45	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
46	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
47	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
48	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
49};
50
51static const struct cmd_control ddr3_cmd_ctrl_data = {
52	.cmd0csratio = MT41K256M16HA125E_RATIO,
53	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
54
55	.cmd1csratio = MT41K256M16HA125E_RATIO,
56	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
57
58	.cmd2csratio = MT41K256M16HA125E_RATIO,
59	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
60};
61
62static struct emif_regs ddr3_emif_reg_data = {
63	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
64	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
65	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
66	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
67	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
68	.zq_config = MT41K256M16HA125E_ZQ_CFG,
69	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
70};
71
72static const struct ctrl_ioregs ddr3_ioregs = {
73	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
74	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
75	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
76	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
77	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
78};
79
80#define OSC	(V_OSCK / 1000000)
81const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
82
83void am33xx_spl_board_init(void)
84{
85	int rc;
86
87	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
88	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
89	/*
90	 * enable additional clocks of modules which are accessed later from
91	 * VxWorks OS
92	 */
93	u32 *const clk_domains[] = { 0 };
94
95	u32 *const clk_modules_xre1specific[] = {
96		&cmwkup->wkup_adctscctrl,
97		&cmper->spi1clkctrl,
98		&cmper->dcan0clkctrl,
99		&cmper->dcan1clkctrl,
100		&cmper->epwmss0clkctrl,
101		&cmper->epwmss1clkctrl,
102		&cmper->epwmss2clkctrl,
103		&cmper->lcdclkctrl,
104		&cmper->lcdcclkstctrl,
105		0
106	};
107	do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
108	/* power-OFF LCD-Display */
109	if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
110		printf("cannot request gpio for LCD_PWR!\n");
111	else if (gpio_direction_output(LCD_PWR, 0) != 0)
112		printf("cannot set direction output on LCD_PWR!\n");
113
114	/* setup I2C */
115	enable_i2c_pin_mux();
116
117	/* power-ON 3V3 via Resetcontroller */
118	rc = br_resetc_regset(RSTCTRL_CTRLREG,
119			      RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB);
120	if (rc != 0)
121		printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");
122
123	pmicsetup(0, 0);
124}
125
126const struct dpll_params *get_dpll_ddr_params(void)
127{
128	return &dpll_ddr3;
129}
130
131void sdram_init(void)
132{
133	config_ddr(400, &ddr3_ioregs,
134		   &ddr3_data,
135		   &ddr3_cmd_ctrl_data,
136		   &ddr3_emif_reg_data, 0);
137}
138#endif /* CONFIG_SPL_BUILD */
139/*
140 * Basic board specific setup.  Pinmux has been handled already.
141 */
142int board_init(void)
143{
144	/* request common used gpios */
145	gpio_request(ESC_KEY, "boot-key");
146
147	if (power_tps65217_init(0))
148		printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
149
150	return 0;
151}
152
153#ifdef CONFIG_BOARD_LATE_INIT
154
155int board_boot_key(void)
156{
157	return gpio_get_value(ESC_KEY);
158}
159
160int board_late_init(void)
161{
162	char othbootargs[128];
163
164	br_resetc_bmode();
165
166	/* setup othbootargs for bootvx-command (vxWorks bootline) */
167	snprintf(othbootargs, sizeof(othbootargs),
168		 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
169		 (u32)gd->relocaddr,
170		 (u32)env_get_ulong("vx_memtop", 16, gd->relocaddr),
171		 (u32)env_get_ulong("vx_romfsbase", 16, 0),
172		 (u32)env_get_ulong("vx_romfssize", 16, 0));
173	env_set("othbootargs", othbootargs);
174	/*
175	 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
176	 * expect that vectors are there, original u-boot moves them to _start
177	 */
178	__asm__("ldr r0,=0x20000");
179	__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
180
181	return 0;
182}
183#endif /* CONFIG_BOARD_LATE_INIT */
184