1menu "Xtensa architecture" 2 depends on XTENSA 3 4config SYS_ARCH 5 string 6 default "xtensa" 7 8config SYS_CPU 9 string "Xtensa Core Variant" 10 11choice 12 prompt "Target select" 13 14config TARGET_XTFPGA 15 bool "Support XTFPGA" 16 select BOARD_POSTCLK_INIT 17 18endchoice 19 20config SYS_ICACHE_OFF 21 bool "Do not enable icache" 22 help 23 Do not enable instruction cache in U-Boot. 24 25config SPL_SYS_ICACHE_OFF 26 bool "Do not enable icache in SPL" 27 depends on SPL 28 default SYS_ICACHE_OFF 29 help 30 Do not enable instruction cache in SPL. 31 32config SYS_DCACHE_OFF 33 bool "Do not enable dcache" 34 help 35 Do not enable data cache in U-Boot. 36 37config SPL_SYS_DCACHE_OFF 38 bool "Do not enable dcache in SPL" 39 depends on SPL 40 default SYS_DCACHE_OFF 41 help 42 Do not enable data cache in SPL. 43 44source "board/cadence/xtfpga/Kconfig" 45 46endmenu 47