1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018 Google, Inc 4 */ 5 6#define LOG_CATEGORY LOGC_BOOT 7 8#include <common.h> 9#include <debug_uart.h> 10#include <dm.h> 11#include <hang.h> 12#include <image.h> 13#include <init.h> 14#include <log.h> 15#include <spl.h> 16#include <asm/cpu.h> 17#include <asm/global_data.h> 18#include <asm/mtrr.h> 19#include <asm/processor.h> 20#include <asm-generic/sections.h> 21 22DECLARE_GLOBAL_DATA_PTR; 23 24static int x86_tpl_init(void) 25{ 26 int ret; 27 28 debug("%s starting\n", __func__); 29 ret = x86_cpu_init_tpl(); 30 if (ret) { 31 debug("%s: x86_cpu_init_tpl() failed\n", __func__); 32 return ret; 33 } 34 ret = spl_init(); 35 if (ret) { 36 debug("%s: spl_init() failed\n", __func__); 37 return ret; 38 } 39 ret = arch_cpu_init(); 40 if (ret) { 41 debug("%s: arch_cpu_init() failed\n", __func__); 42 return ret; 43 } 44 preloader_console_init(); 45 46 return 0; 47} 48 49void board_init_f(ulong flags) 50{ 51 int ret; 52 53 ret = x86_tpl_init(); 54 if (ret) { 55 debug("Error %d\n", ret); 56 panic("x86_tpl_init fail"); 57 } 58 59 /* Uninit CAR and jump to board_init_f_r() */ 60 board_init_r(gd, 0); 61} 62 63void board_init_f_r(void) 64{ 65 /* Not used since we never call board_init_f_r_trampoline() */ 66 while (1); 67} 68 69u32 spl_boot_device(void) 70{ 71 return IS_ENABLED(CONFIG_CHROMEOS_VBOOT) ? BOOT_DEVICE_CROS_VBOOT : 72 BOOT_DEVICE_SPI_MMAP; 73} 74 75int spl_start_uboot(void) 76{ 77 return 0; 78} 79 80void spl_board_announce_boot_device(void) 81{ 82 printf("SPI flash"); 83} 84 85static int spl_board_load_image(struct spl_image_info *spl_image, 86 struct spl_boot_device *bootdev) 87{ 88 spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ 89 spl_image->entry_point = CONFIG_SPL_TEXT_BASE; 90 spl_image->load_addr = CONFIG_SPL_TEXT_BASE; 91 spl_image->os = IH_OS_U_BOOT; 92 spl_image->name = "U-Boot"; 93 94 debug("Loading to %lx\n", spl_image->load_addr); 95 96 return 0; 97} 98SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image); 99 100int spl_spi_load_image(void) 101{ 102 return -EPERM; 103} 104 105void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) 106{ 107 debug("Jumping to %s at %lx\n", spl_phase_name(spl_next_phase()), 108 (ulong)spl_image->entry_point); 109#ifdef DEBUG 110 print_buffer(spl_image->entry_point, (void *)spl_image->entry_point, 1, 111 0x20, 0); 112#endif 113 jump_to_spl(spl_image->entry_point); 114 hang(); 115} 116 117void spl_board_init(void) 118{ 119 preloader_console_init(); 120} 121 122#if !CONFIG_IS_ENABLED(PCI) 123/* 124 * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough 125 * to bind the devices on the PCI bus, some of which have early-regs properties 126 * providing fixed BARs. Individual drivers program these BARs themselves so 127 * that they can access the devices. The BARs are allocated statically in the 128 * device tree. 129 * 130 * Once SPL is running it enables PCI properly, but does not auto-assign BARs 131 * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does 132 * the auto allocation (after relocation). 133 */ 134#if CONFIG_IS_ENABLED(OF_REAL) 135static const struct udevice_id tpl_fake_pci_ids[] = { 136 { .compatible = "pci-x86" }, 137 { } 138}; 139#endif 140 141U_BOOT_DRIVER(pci_x86) = { 142 .name = "pci_x86", 143 .id = UCLASS_SIMPLE_BUS, 144 .of_match = of_match_ptr(tpl_fake_pci_ids), 145 DM_PHASE(tpl) 146}; 147#endif 148