1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2013 Google Inc.
4 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
5 *
6 * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
7 */
8
9#ifndef _DEVICE_H_
10#define _DEVICE_H_
11
12/*
13 * Internal PCI device numbers within the SoC.
14 *
15 * Note it must start with 0x_ prefix, as the device number macro will be
16 * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
17 */
18
19/* SoC transaction router */
20#define SOC_DEV		0x00
21
22/* Graphics and Display */
23#define GFX_DEV		0x02
24
25/* MIPI */
26#define MIPI_DEV	0x03
27
28/* EMMC Port */
29#define EMMC_DEV	0x10
30
31/* SDIO Port */
32#define SDIO_DEV	0x11
33
34/* SD Port */
35#define SD_DEV		0x12
36
37/* SATA */
38#define SATA_DEV	0x13
39
40/* xHCI */
41#define XHCI_DEV	0x14
42
43/* LPE Audio */
44#define LPE_DEV		0x15
45
46/* OTG */
47#define OTG_DEV		0x16
48
49/* MMC45 Port */
50#define MMC45_DEV	0x17
51
52/* Serial IO 1 */
53#define SIO1_DEV	0x18
54
55/* Trusted Execution Engine */
56#define TXE_DEV		0x1a
57
58/* HD Audio */
59#define HDA_DEV		0x1b
60
61/* PCIe Ports */
62#define PCIE_DEV	0x1c
63
64/* EHCI */
65#define EHCI_DEV	0x1d
66
67/* Serial IO 2 */
68#define SIO2_DEV	0x1e
69
70/* Platform Controller Unit */
71#define PCU_DEV		0x1f
72
73#endif /* _DEVICE_H_ */
74